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Neil Armstrongf9e60542019-03-08 15:09:40 +01001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
4 */
5
Jerome Brunetdd5f2352020-03-05 12:12:38 +01006#include "meson-g12.dtsi"
Neil Armstrongf9e60542019-03-08 15:09:40 +01007
8/ {
9 compatible = "amlogic,g12a";
10
Neil Armstrongf9e60542019-03-08 15:09:40 +010011 cpus {
12 #address-cells = <0x2>;
13 #size-cells = <0x0>;
14
15 cpu0: cpu@0 {
16 device_type = "cpu";
17 compatible = "arm,cortex-a53";
18 reg = <0x0 0x0>;
19 enable-method = "psci";
20 next-level-cache = <&l2>;
Jerome Brunetdd5f2352020-03-05 12:12:38 +010021 #cooling-cells = <2>;
Neil Armstrongf9e60542019-03-08 15:09:40 +010022 };
23
24 cpu1: cpu@1 {
25 device_type = "cpu";
26 compatible = "arm,cortex-a53";
27 reg = <0x0 0x1>;
28 enable-method = "psci";
29 next-level-cache = <&l2>;
Jerome Brunetdd5f2352020-03-05 12:12:38 +010030 #cooling-cells = <2>;
Neil Armstrongf9e60542019-03-08 15:09:40 +010031 };
32
33 cpu2: cpu@2 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53";
36 reg = <0x0 0x2>;
37 enable-method = "psci";
38 next-level-cache = <&l2>;
Jerome Brunetdd5f2352020-03-05 12:12:38 +010039 #cooling-cells = <2>;
Neil Armstrongf9e60542019-03-08 15:09:40 +010040 };
41
42 cpu3: cpu@3 {
43 device_type = "cpu";
44 compatible = "arm,cortex-a53";
45 reg = <0x0 0x3>;
46 enable-method = "psci";
47 next-level-cache = <&l2>;
Jerome Brunetdd5f2352020-03-05 12:12:38 +010048 #cooling-cells = <2>;
Neil Armstrongf9e60542019-03-08 15:09:40 +010049 };
50
51 l2: l2-cache0 {
52 compatible = "cache";
53 };
54 };
55
Andreas Färber1a87cc72019-10-09 16:03:54 +020056 cpu_opp_table: opp-table {
57 compatible = "operating-points-v2";
58 opp-shared;
Neil Armstrongb1e81e62019-05-28 10:50:36 +020059
Andreas Färber1a87cc72019-10-09 16:03:54 +020060 opp-100000000 {
61 opp-hz = /bits/ 64 <100000000>;
62 opp-microvolt = <731000>;
Neil Armstrongf9e60542019-03-08 15:09:40 +010063 };
Neil Armstrongb1e81e62019-05-28 10:50:36 +020064
Andreas Färber1a87cc72019-10-09 16:03:54 +020065 opp-250000000 {
66 opp-hz = /bits/ 64 <250000000>;
67 opp-microvolt = <731000>;
68 };
69
70 opp-500000000 {
71 opp-hz = /bits/ 64 <500000000>;
72 opp-microvolt = <731000>;
73 };
74
75 opp-667000000 {
76 opp-hz = /bits/ 64 <666666666>;
77 opp-microvolt = <731000>;
78 };
79
80 opp-1000000000 {
81 opp-hz = /bits/ 64 <1000000000>;
82 opp-microvolt = <731000>;
83 };
84
85 opp-1200000000 {
86 opp-hz = /bits/ 64 <1200000000>;
87 opp-microvolt = <731000>;
88 };
89
90 opp-1398000000 {
91 opp-hz = /bits/ 64 <1398000000>;
92 opp-microvolt = <761000>;
93 };
94
95 opp-1512000000 {
96 opp-hz = /bits/ 64 <1512000000>;
97 opp-microvolt = <791000>;
98 };
99
100 opp-1608000000 {
101 opp-hz = /bits/ 64 <1608000000>;
102 opp-microvolt = <831000>;
103 };
104
105 opp-1704000000 {
106 opp-hz = /bits/ 64 <1704000000>;
107 opp-microvolt = <861000>;
108 };
109
110 opp-1800000000 {
111 opp-hz = /bits/ 64 <1800000000>;
112 opp-microvolt = <981000>;
Neil Armstrongb1e81e62019-05-28 10:50:36 +0200113 };
114 };
Andreas Färber1a87cc72019-10-09 16:03:54 +0200115};
Neil Armstrongb1e81e62019-05-28 10:50:36 +0200116
Jerome Brunetdd5f2352020-03-05 12:12:38 +0100117&cpu_thermal {
118 cooling-maps {
119 map0 {
120 trip = <&cpu_passive>;
121 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
122 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
123 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
124 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
125 };
Neil Armstrongf9e60542019-03-08 15:09:40 +0100126
Jerome Brunetdd5f2352020-03-05 12:12:38 +0100127 map1 {
128 trip = <&cpu_hot>;
129 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
130 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
131 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
132 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
133 };
134 };
Neil Armstrongf9e60542019-03-08 15:09:40 +0100135};