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Chris Zankelc978b522016-08-10 18:36:44 +03001menu "Xtensa architecture"
2 depends on XTENSA
3
4config SYS_ARCH
5 string
6 default "xtensa"
7
8config SYS_CPU
9 string "Xtensa Core Variant"
10
11choice
12 prompt "Target select"
13
Chris Zankel7e270ec2016-08-10 18:36:48 +030014config TARGET_XTFPGA
15 bool "Support XTFPGA"
Chris Zankelc978b522016-08-10 18:36:44 +030016
17endchoice
18
Trevor Woernera0aba8a2019-05-03 09:40:59 -040019config SYS_ICACHE_OFF
20 bool "Do not enable icache"
21 default n
22 help
23 Do not enable instruction cache in U-Boot.
24
Trevor Woerner10015022019-05-03 09:41:00 -040025config SPL_SYS_ICACHE_OFF
26 bool "Do not enable icache in SPL"
27 depends on SPL
28 default SYS_ICACHE_OFF
29 help
30 Do not enable instruction cache in SPL.
31
Trevor Woernera0aba8a2019-05-03 09:40:59 -040032config SYS_DCACHE_OFF
33 bool "Do not enable dcache"
34 default n
35 help
36 Do not enable data cache in U-Boot.
37
Trevor Woerner10015022019-05-03 09:41:00 -040038config SPL_SYS_DCACHE_OFF
39 bool "Do not enable dcache in SPL"
40 depends on SPL
41 default SYS_DCACHE_OFF
42 help
43 Do not enable data cache in SPL.
44
Chris Zankel7e270ec2016-08-10 18:36:48 +030045source "board/cadence/xtfpga/Kconfig"
Chris Zankelc978b522016-08-10 18:36:44 +030046
47endmenu