blob: 95085611336af8d32c5940306bcd6d40958fe9d6 [file] [log] [blame]
Kumar Gala33b90792008-08-26 23:15:28 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
Paul Gortmaker3e3262b2011-12-30 23:53:12 -050010#include <i2c.h>
Kumar Gala33b90792008-08-26 23:15:28 -050011
12#include <asm/fsl_ddr_sdram.h>
Haiying Wangdfb49102008-10-03 12:36:55 -040013#include <asm/fsl_ddr_dimm_params.h>
Kumar Gala33b90792008-08-26 23:15:28 -050014
Haiying Wangdfb49102008-10-03 12:36:55 -040015void fsl_ddr_board_options(memctl_options_t *popts,
16 dimm_params_t *pdimm,
17 unsigned int ctrl_num)
Kumar Gala33b90792008-08-26 23:15:28 -050018{
19 /*
20 * Factors to consider for clock adjust:
21 * - number of chips on bus
22 * - position of slot
23 * - DDR1 vs. DDR2?
24 * - ???
25 *
26 * This needs to be determined on a board-by-board basis.
27 * 0110 3/4 cycle late
28 * 0111 7/8 cycle late
29 */
30 popts->clk_adjust = 7;
31
32 /*
33 * Factors to consider for CPO:
34 * - frequency
35 * - ddr1 vs. ddr2
36 */
37 popts->cpo_override = 10;
38
39 /*
40 * Factors to consider for write data delay:
41 * - number of DIMMs
42 *
43 * 1 = 1/4 clock delay
44 * 2 = 1/2 clock delay
45 * 3 = 3/4 clock delay
46 * 4 = 1 clock delay
47 * 5 = 5/4 clock delay
48 * 6 = 3/2 clock delay
49 */
50 popts->write_data_delay = 3;
51
52 /*
53 * Factors to consider for half-strength driver enable:
54 * - number of DIMMs installed
55 */
56 popts->half_strength_driver_enable = 0;
57}
Paul Gortmaker2a6b3b72011-12-30 23:53:11 -050058
Paul Gortmaker3e3262b2011-12-30 23:53:12 -050059#ifdef CONFIG_SPD_EEPROM
60/*
61 * Workaround for hardware errata. An i2c address conflict
62 * existed on earlier boards; the workaround moved the DDR
63 * SPD from 0x51 to 0x53. So we try and read 0x53 1st, and
64 * if that fails, then fall back to reading at 0x51.
65 */
66void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
67{
68 int ret;
69
70#ifdef ALT_SPD_EEPROM_ADDRESS
71 if (i2c_address == SPD_EEPROM_ADDRESS) {
72 ret = i2c_read(ALT_SPD_EEPROM_ADDRESS, 0, 1, (uchar *)spd,
73 sizeof(generic_spd_eeprom_t));
74 if (ret == 0)
75 return; /* Good data at 0x53 */
76 memset(spd, 0, sizeof(generic_spd_eeprom_t));
77 }
78#endif
79 ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
80 sizeof(generic_spd_eeprom_t));
81 if (ret) {
82 printf("DDR: failed to read SPD from addr %u\n", i2c_address);
83 memset(spd, 0, sizeof(generic_spd_eeprom_t));
84 }
85}
86
87#else
Paul Gortmaker2a6b3b72011-12-30 23:53:11 -050088/*
89 * fixed_sdram init -- doesn't use serial presence detect.
90 * Assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed.
91 */
92phys_size_t fixed_sdram(void)
93{
Andy Fleminge76cd5d2012-10-23 19:03:46 -050094 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
Paul Gortmaker2a6b3b72011-12-30 23:53:11 -050095
96 out_be32(&ddr->cs0_bnds, 0x0000007f);
97 out_be32(&ddr->cs1_bnds, 0x008000ff);
98 out_be32(&ddr->cs2_bnds, 0x00000000);
99 out_be32(&ddr->cs3_bnds, 0x00000000);
100
101 out_be32(&ddr->cs0_config, 0x80010101);
102 out_be32(&ddr->cs1_config, 0x80010101);
103 out_be32(&ddr->cs2_config, 0x00000000);
104 out_be32(&ddr->cs3_config, 0x00000000);
105
106 out_be32(&ddr->timing_cfg_3, 0x00000000);
107 out_be32(&ddr->timing_cfg_0, 0x00220802);
108 out_be32(&ddr->timing_cfg_1, 0x38377322);
109 out_be32(&ddr->timing_cfg_2, 0x0fa044C7);
110
111 out_be32(&ddr->sdram_cfg, 0x4300C000);
112 out_be32(&ddr->sdram_cfg_2, 0x24401000);
113
114 out_be32(&ddr->sdram_mode, 0x23C00542);
115 out_be32(&ddr->sdram_mode_2, 0x00000000);
116
117 out_be32(&ddr->sdram_interval, 0x05080100);
118 out_be32(&ddr->sdram_md_cntl, 0x00000000);
119 out_be32(&ddr->sdram_data_init, 0x00000000);
120 out_be32(&ddr->sdram_clk_cntl, 0x03800000);
121 asm("sync;isync;msync");
122 udelay(500);
123
124 #ifdef CONFIG_DDR_ECC
125 /* Enable ECC checking */
126 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | 0x20000000);
127 #else
128 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
129 #endif
130
131 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
132}
133#endif