blob: 1e5b501ab1abe8a5d055f4ec8379738499daeb81 [file] [log] [blame]
Mingkai Hua8d97582013-07-04 17:33:43 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
York Sun3aab0cd2013-08-12 14:57:12 -07004 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hua8d97582013-07-04 17:33:43 +08005 */
6
7/*
8 * C29XPCIE board configuration file
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_PHYS_64BIT
Chunhe Lan9a7eeb92014-11-07 15:39:56 +080015#define CONFIG_DISPLAY_BOARDINFO
Mingkai Hua8d97582013-07-04 17:33:43 +080016
17#ifdef CONFIG_C29XPCIE
18#define CONFIG_PPC_C29X
19#endif
20
21#ifdef CONFIG_SPIFLASH
22#define CONFIG_RAMBOOT_SPIFLASH
23#define CONFIG_SYS_TEXT_BASE 0x11000000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053024#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
Mingkai Hua8d97582013-07-04 17:33:43 +080025#endif
26
Po Liueb6b4582014-01-10 10:10:59 +080027#ifdef CONFIG_NAND
Po Liueb6b4582014-01-10 10:10:59 +080028#ifdef CONFIG_TPL_BUILD
29#define CONFIG_SPL_NAND_BOOT
30#define CONFIG_SPL_FLUSH_IMAGE
31#define CONFIG_SPL_ENV_SUPPORT
32#define CONFIG_SPL_NAND_INIT
33#define CONFIG_SPL_SERIAL_SUPPORT
34#define CONFIG_SPL_LIBGENERIC_SUPPORT
35#define CONFIG_SPL_LIBCOMMON_SUPPORT
36#define CONFIG_SPL_I2C_SUPPORT
37#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
38#define CONFIG_SPL_NAND_SUPPORT
39#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
40#define CONFIG_SPL_COMMON_INIT_DDR
41#define CONFIG_SPL_MAX_SIZE (128 << 10)
42#define CONFIG_SPL_TEXT_BASE 0xf8f81000
43#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053044#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Po Liueb6b4582014-01-10 10:10:59 +080045#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
46#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
47#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
48#elif defined(CONFIG_SPL_BUILD)
49#define CONFIG_SPL_INIT_MINIMAL
50#define CONFIG_SPL_SERIAL_SUPPORT
51#define CONFIG_SPL_NAND_SUPPORT
52#define CONFIG_SPL_NAND_MINIMAL
53#define CONFIG_SPL_FLUSH_IMAGE
54#define CONFIG_SPL_TEXT_BASE 0xff800000
55#define CONFIG_SPL_MAX_SIZE 8192
56#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
57#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
58#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
59#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
60#endif
61#define CONFIG_SPL_PAD_TO 0x20000
62#define CONFIG_TPL_PAD_TO 0x20000
63#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
64#define CONFIG_SYS_TEXT_BASE 0x11001000
65#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
66#endif
67
Mingkai Hua8d97582013-07-04 17:33:43 +080068#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053069#define CONFIG_SYS_TEXT_BASE 0xeff40000
Mingkai Hua8d97582013-07-04 17:33:43 +080070#endif
71
72#ifndef CONFIG_RESET_VECTOR_ADDRESS
73#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
74#endif
75
Po Liueb6b4582014-01-10 10:10:59 +080076#ifdef CONFIG_SPL_BUILD
77#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
78#else
79#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
80#endif
81
82#ifdef CONFIG_SPL_BUILD
83#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
Mingkai Hua8d97582013-07-04 17:33:43 +080084#endif
85
86/* High Level Configuration Options */
87#define CONFIG_BOOKE /* BOOKE */
88#define CONFIG_E500 /* BOOKE e500 family */
Mingkai Hua8d97582013-07-04 17:33:43 +080089#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053090#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Mingkai Hua8d97582013-07-04 17:33:43 +080091#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */
92
93#define CONFIG_PCI /* Enable PCI/PCIE */
94#ifdef CONFIG_PCI
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040095#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
Mingkai Hua8d97582013-07-04 17:33:43 +080096#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
97#define CONFIG_PCI_INDIRECT_BRIDGE
98#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
99#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
100
Mingkai Hua8d97582013-07-04 17:33:43 +0800101#define CONFIG_CMD_PCI
102
Mingkai Hua8d97582013-07-04 17:33:43 +0800103/*
104 * PCI Windows
105 * Memory space is mapped 1-1, but I/O space must start from 0.
106 */
107/* controller 1, Slot 1, tgtid 1, Base address a000 */
108#define CONFIG_SYS_PCIE1_NAME "Slot 1"
109#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
110#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
111#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
112#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
113#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
114#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
115#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
116#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
117
118#define CONFIG_PCI_PNP /* do pci plug-and-play */
119
120#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
121#define CONFIG_DOS_PARTITION
122#endif
123
124#define CONFIG_FSL_LAW /* Use common FSL init code */
125#define CONFIG_TSEC_ENET
126#define CONFIG_ENV_OVERWRITE
127
128#define CONFIG_DDR_CLK_FREQ 100000000
129#define CONFIG_SYS_CLK_FREQ 66666666
130
131#define CONFIG_HWCONFIG
132
133/*
134 * These can be toggled for performance analysis, otherwise use default.
135 */
136#define CONFIG_L2_CACHE /* toggle L2 cache */
137#define CONFIG_BTB /* toggle branch predition */
138
139#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
140
141#define CONFIG_ENABLE_36BIT_PHYS
142
143#define CONFIG_ADDR_MAP 1
144#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
145
146#define CONFIG_SYS_MEMTEST_START 0x00200000
147#define CONFIG_SYS_MEMTEST_END 0x00400000
148#define CONFIG_PANIC_HANG
149
150/* DDR Setup */
York Sun5614e712013-09-30 09:22:09 -0700151#define CONFIG_SYS_FSL_DDR3
Mingkai Hua8d97582013-07-04 17:33:43 +0800152#define CONFIG_DDR_SPD
153#define CONFIG_SYS_SPD_BUS_NUM 0
154#define SPD_EEPROM_ADDRESS 0x50
155#define CONFIG_SYS_DDR_RAW_TIMING
156
157/* DDR ECC Setup*/
158#define CONFIG_DDR_ECC
159#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
160#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
161
162#define CONFIG_SYS_SDRAM_SIZE 512
163#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
164#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
165
166#define CONFIG_DIMM_SLOTS_PER_CTLR 1
167#define CONFIG_CHIP_SELECTS_PER_CTRL 1
168
169#define CONFIG_SYS_CCSRBAR 0xffe00000
170#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
171
172/* Platform SRAM setting */
173#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000
174#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \
175 (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE)
176#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10)
177
Po Liueb6b4582014-01-10 10:10:59 +0800178#ifdef CONFIG_SPL_BUILD
179#define CONFIG_SYS_NO_FLASH
180#endif
181
Mingkai Hua8d97582013-07-04 17:33:43 +0800182/*
183 * IFC Definitions
184 */
185/* NOR Flash on IFC */
186#define CONFIG_SYS_FLASH_BASE 0xec000000
187#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
188
189#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
190
191#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
192#define CONFIG_SYS_MAX_FLASH_BANKS 1
193
194#define CONFIG_SYS_FLASH_QUIET_TEST
195#define CONFIG_FLASH_SHOW_PROGRESS 45
196#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */
197#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */
198
199/* 16Bit NOR Flash - S29GL512S10TFI01 */
200#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
201 CSPR_PORT_SIZE_16 | \
202 CSPR_MSEL_NOR | \
203 CSPR_V)
204#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024)
205#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4)
Po Liuac2785c2013-08-21 14:22:18 +0800206
Mingkai Hua8d97582013-07-04 17:33:43 +0800207#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
208 FTIM0_NOR_TEADC(0x5) | \
209 FTIM0_NOR_TEAHC(0x5))
Po Liuac2785c2013-08-21 14:22:18 +0800210#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
211 FTIM1_NOR_TRAD_NOR(0x1A) |\
212 FTIM1_NOR_TSEQRAD_NOR(0x13))
Mingkai Hua8d97582013-07-04 17:33:43 +0800213#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
214 FTIM2_NOR_TCH(0x4) | \
Po Liuac2785c2013-08-21 14:22:18 +0800215 FTIM2_NOR_TWPH(0x0E) | \
Mingkai Hua8d97582013-07-04 17:33:43 +0800216 FTIM2_NOR_TWP(0x1c))
217#define CONFIG_SYS_NOR_FTIM3 0x0
218
219/* CFI for NOR Flash */
220#define CONFIG_FLASH_CFI_DRIVER
221#define CONFIG_SYS_FLASH_CFI
222#define CONFIG_SYS_FLASH_EMPTY_INFO
223#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
224
225/* NAND Flash on IFC */
226#define CONFIG_NAND_FSL_IFC
227#define CONFIG_SYS_NAND_BASE 0xff800000
228#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
229
230#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
231
232#define CONFIG_SYS_MAX_NAND_DEVICE 1
Mingkai Hua8d97582013-07-04 17:33:43 +0800233#define CONFIG_CMD_NAND
Po Liueb6b4582014-01-10 10:10:59 +0800234#define CONFIG_SYS_NAND_BLOCK_SIZE (1024 * 1024)
Mingkai Hua8d97582013-07-04 17:33:43 +0800235
236/* 8Bit NAND Flash - K9F1G08U0B */
237#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
238 | CSPR_PORT_SIZE_8 \
239 | CSPR_MSEL_NAND \
240 | CSPR_V)
241#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
Prabhakar Kushwahaaffd5202013-10-04 10:05:50 +0530242#define CONFIG_SYS_NAND_OOBSIZE 0x00000280 /* 640b */
Mingkai Hua8d97582013-07-04 17:33:43 +0800243#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
244 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
245 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
Prabhakar Kushwahaaffd5202013-10-04 10:05:50 +0530246 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
247 | CSOR_NAND_PGS_8K /* Page Size = 8K */ \
248 | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\
249 | CSOR_NAND_PB(128)) /*128 Pages Per Block*/
Mingkai Hua8d97582013-07-04 17:33:43 +0800250#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \
251 FTIM0_NAND_TWP(0x0c) | \
252 FTIM0_NAND_TWCHT(0x08) | \
253 FTIM0_NAND_TWH(0x06))
254#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \
255 FTIM1_NAND_TWBE(0x1d) | \
256 FTIM1_NAND_TRR(0x08) | \
257 FTIM1_NAND_TRP(0x0c))
258#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \
259 FTIM2_NAND_TREH(0x0a) | \
260 FTIM2_NAND_TWHRE(0x18))
261#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04))
262
263#define CONFIG_SYS_NAND_DDR_LAW 11
264
265/* Set up IFC registers for boot location NOR/NAND */
Po Liueb6b4582014-01-10 10:10:59 +0800266#ifdef CONFIG_NAND
267#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
268#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
269#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
270#define CONFIG_SYS_CSOR0_EXT CONFIG_SYS_NAND_OOBSIZE
271#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
272#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
273#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
274#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
275#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
276#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
277#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
278#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
279#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
280#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
281#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
282#else
Mingkai Hua8d97582013-07-04 17:33:43 +0800283#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
284#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
285#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
286#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
287#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
288#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
289#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
290#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
291#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
292#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
Prabhakar Kushwahaaffd5202013-10-04 10:05:50 +0530293#define CONFIG_SYS_CSOR1_EXT CONFIG_SYS_NAND_OOBSIZE
Mingkai Hua8d97582013-07-04 17:33:43 +0800294#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
295#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
296#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
297#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
Po Liueb6b4582014-01-10 10:10:59 +0800298#endif
Mingkai Hua8d97582013-07-04 17:33:43 +0800299
300/* CPLD on IFC, selected by CS2 */
301#define CONFIG_SYS_CPLD_BASE 0xffdf0000
302#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \
303 | CONFIG_SYS_CPLD_BASE)
304
305#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
306 | CSPR_PORT_SIZE_8 \
307 | CSPR_MSEL_GPCM \
308 | CSPR_V)
309#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
310#define CONFIG_SYS_CSOR2 0x0
311/* CPLD Timing parameters for IFC CS2 */
312#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
313 FTIM0_GPCM_TEADC(0x0e) | \
314 FTIM0_GPCM_TEAHC(0x0e))
315#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
316 FTIM1_GPCM_TRAD(0x1f))
317#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800318 FTIM2_GPCM_TCH(0x8) | \
Mingkai Hua8d97582013-07-04 17:33:43 +0800319 FTIM2_GPCM_TWP(0x1f))
320#define CONFIG_SYS_CS2_FTIM3 0x0
321
322#if defined(CONFIG_RAMBOOT_SPIFLASH)
323#define CONFIG_SYS_RAMBOOT
324#define CONFIG_SYS_EXTRA_ENV_RELOC
325#endif
326
327#define CONFIG_BOARD_EARLY_INIT_R
328
329#define CONFIG_SYS_INIT_RAM_LOCK
330#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000
York Sunb39d1212016-04-06 13:22:10 -0700331#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Mingkai Hua8d97582013-07-04 17:33:43 +0800332
York Sunb39d1212016-04-06 13:22:10 -0700333#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
Mingkai Hua8d97582013-07-04 17:33:43 +0800334 - GENERATED_GBL_DATA_SIZE)
335#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
336
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530337#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Po Liueb6b4582014-01-10 10:10:59 +0800338#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024)
339
340/*
341 * Config the L2 Cache as L2 SRAM
342 */
343#if defined(CONFIG_SPL_BUILD)
344#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
345#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
346#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
347#define CONFIG_SYS_L2_SIZE (256 << 10)
348#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
349#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
350#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024)
351#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
352#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024)
353#define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10)
354#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
355#elif defined(CONFIG_NAND)
356#ifdef CONFIG_TPL_BUILD
357#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
358#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
359#define CONFIG_SYS_L2_SIZE (256 << 10)
360#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
361#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
362#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
363#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
364#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
365#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
366#else
367#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
368#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
369#define CONFIG_SYS_L2_SIZE (256 << 10)
370#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
371#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000)
372#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
373#endif
374#endif
375#endif
Mingkai Hua8d97582013-07-04 17:33:43 +0800376
377/* Serial Port */
378#define CONFIG_CONS_INDEX 1
Mingkai Hua8d97582013-07-04 17:33:43 +0800379#define CONFIG_SYS_NS16550_SERIAL
380#define CONFIG_SYS_NS16550_REG_SIZE 1
381#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
382
Po Liueb6b4582014-01-10 10:10:59 +0800383#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
384#define CONFIG_NS16550_MIN_FUNCTIONS
385#endif
386
Mingkai Hua8d97582013-07-04 17:33:43 +0800387#define CONFIG_SYS_CONSOLE_IS_IN_ENV
388
389#define CONFIG_SYS_BAUDRATE_TABLE \
390 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
391
392#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
393#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
394
Mingkai Hua8d97582013-07-04 17:33:43 +0800395#define CONFIG_SYS_I2C
396#define CONFIG_SYS_I2C_FSL
397#define CONFIG_SYS_FSL_I2C_SPEED 400000
398#define CONFIG_SYS_FSL_I2C2_SPEED 400000
399#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
400#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
401#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
402#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
403
404/* I2C EEPROM */
405/* enable read and write access to EEPROM */
406#define CONFIG_CMD_EEPROM
Mingkai Hua8d97582013-07-04 17:33:43 +0800407#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
408#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
409#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
410
Mingkai Hua8d97582013-07-04 17:33:43 +0800411/* eSPI - Enhanced SPI */
Mingkai Hua8d97582013-07-04 17:33:43 +0800412#define CONFIG_SF_DEFAULT_SPEED 10000000
413#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
414
415#ifdef CONFIG_TSEC_ENET
Mingkai Hua8d97582013-07-04 17:33:43 +0800416#define CONFIG_MII /* MII PHY management */
417#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
418#define CONFIG_TSEC1 1
419#define CONFIG_TSEC1_NAME "eTSEC1"
420#define CONFIG_TSEC2 1
421#define CONFIG_TSEC2_NAME "eTSEC2"
422
423/* Default mode is RGMII mode */
424#define TSEC1_PHY_ADDR 0
425#define TSEC2_PHY_ADDR 2
426
427#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
428#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
429
430#define CONFIG_ETHPRIME "eTSEC1"
431
432#define CONFIG_PHY_GIGE
433#endif /* CONFIG_TSEC_ENET */
434
435/*
436 * Environment
437 */
438#if defined(CONFIG_SYS_RAMBOOT)
439#if defined(CONFIG_RAMBOOT_SPIFLASH)
440#define CONFIG_ENV_IS_IN_SPI_FLASH
441#define CONFIG_ENV_SPI_BUS 0
442#define CONFIG_ENV_SPI_CS 0
443#define CONFIG_ENV_SPI_MAX_HZ 10000000
444#define CONFIG_ENV_SPI_MODE 0
445#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
446#define CONFIG_ENV_SECT_SIZE 0x10000
447#define CONFIG_ENV_SIZE 0x2000
448#endif
Po Liueb6b4582014-01-10 10:10:59 +0800449#elif defined(CONFIG_NAND)
450#define CONFIG_ENV_IS_IN_NAND
451#ifdef CONFIG_TPL_BUILD
452#define CONFIG_ENV_SIZE 0x2000
453#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
454#else
455#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
456#define CONFIG_ENV_RANGE CONFIG_ENV_SIZE
457#endif
458#define CONFIG_ENV_OFFSET CONFIG_SYS_NAND_BLOCK_SIZE
Mingkai Hua8d97582013-07-04 17:33:43 +0800459#else
460#define CONFIG_ENV_IS_IN_FLASH
Mingkai Hua8d97582013-07-04 17:33:43 +0800461#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Mingkai Hua8d97582013-07-04 17:33:43 +0800462#define CONFIG_ENV_SIZE 0x2000
463#define CONFIG_ENV_SECT_SIZE 0x20000
464#endif
465
466#define CONFIG_LOADS_ECHO
467#define CONFIG_SYS_LOADS_BAUD_CHANGE
468
469/*
470 * Command line configuration.
471 */
Mingkai Hua8d97582013-07-04 17:33:43 +0800472#define CONFIG_CMD_ERRATA
Mingkai Hua8d97582013-07-04 17:33:43 +0800473#define CONFIG_CMD_IRQ
Mingkai Hua8d97582013-07-04 17:33:43 +0800474#define CONFIG_CMD_REGINFO
475
Ruchika Gupta737537e2014-10-15 11:35:31 +0530476/* Hash command with SHA acceleration supported in hardware */
477#ifdef CONFIG_FSL_CAAM
478#define CONFIG_CMD_HASH
479#define CONFIG_SHA_HW_ACCEL
480#endif
481
Mingkai Hua8d97582013-07-04 17:33:43 +0800482/*
483 * Miscellaneous configurable options
484 */
485#define CONFIG_SYS_LONGHELP /* undef to save memory */
486#define CONFIG_CMDLINE_EDITING /* Command-line editing */
487#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
488#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Mingkai Hua8d97582013-07-04 17:33:43 +0800489
490#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
491#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
492 /* Print Buffer Size */
493#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
494#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Mingkai Hua8d97582013-07-04 17:33:43 +0800495
496/*
497 * For booting Linux, the board info and command line data
498 * have to be in the first 64 MB of memory, since this is
499 * the maximum mapped by the Linux kernel during initialization.
500 */
501#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
502#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
503
504/*
505 * Environment Configuration
506 */
507
508#ifdef CONFIG_TSEC_ENET
509#define CONFIG_HAS_ETH0
510#define CONFIG_HAS_ETH1
511#endif
512
513#define CONFIG_ROOTPATH "/opt/nfsroot"
514#define CONFIG_BOOTFILE "uImage"
515#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */
516
517/* default location for tftp and bootm */
518#define CONFIG_LOADADDR 1000000
519
520#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
521
522#define CONFIG_BAUDRATE 115200
523
Po Liu9c25ee62013-09-26 09:40:11 +0800524#define CONFIG_DEF_HWCONFIG fsl_ddr:ecc=on
525
Mingkai Hua8d97582013-07-04 17:33:43 +0800526#define CONFIG_EXTRA_ENV_SETTINGS \
527 "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
528 "netdev=eth0\0" \
529 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
530 "loadaddr=1000000\0" \
531 "consoledev=ttyS0\0" \
532 "ramdiskaddr=2000000\0" \
533 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
534 "fdtaddr=c00000\0" \
535 "fdtfile=name/of/device-tree.dtb\0" \
536 "othbootargs=ramdisk_size=600000\0" \
537
538#define CONFIG_RAMBOOTCOMMAND \
539 "setenv bootargs root=/dev/ram rw " \
540 "console=$consoledev,$baudrate $othbootargs; " \
541 "tftp $ramdiskaddr $ramdiskfile;" \
542 "tftp $loadaddr $bootfile;" \
543 "tftp $fdtaddr $fdtfile;" \
544 "bootm $loadaddr $ramdiskaddr $fdtaddr"
545
546#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
547
Po Liu3ca49c42014-11-26 09:38:48 +0800548#include <asm/fsl_secure_boot.h>
549
Mingkai Hua8d97582013-07-04 17:33:43 +0800550#endif /* __CONFIG_H */