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Mike Frysingerd7fdc142008-10-12 23:16:52 -04001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for CSP Minotaur board
Mike Frysingerd7fdc142008-10-12 23:16:52 -04003 *
4 * Thu Oct 25 15:30:44 CEST 2007 <hackfin@section5.ch>
5 * Minotaur config, brushed up for official uClinux dist.
6 * Parallel flash support disabled, SPI flash boot command
7 * added ('run flashboot').
8 *
9 * Flash image map:
10 *
11 * 0x00000000 u-boot bootstrap
12 * 0x00010000 environment
13 * 0x00020000 u-boot code
14 * 0x00030000 uImage.initramfs
15 *
16 */
17
18#ifndef __CONFIG_BF537_MINOTAUR_H__
19#define __CONFIG_BF537_MINOTAUR_H__
20
Mike Frysingerf348ab82009-04-24 17:22:40 -040021#include <asm/config-pre.h>
Mike Frysingerd7fdc142008-10-12 23:16:52 -040022
Mike Frysingerd7fdc142008-10-12 23:16:52 -040023/*
24 * Processor Settings
25 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050026#define CONFIG_BFIN_CPU bf537-0.2
Mike Frysingerd7fdc142008-10-12 23:16:52 -040027#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
28
Mike Frysingerd7fdc142008-10-12 23:16:52 -040029/*
30 * Clock Settings
31 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
32 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
33 */
34/* CONFIG_CLKIN_HZ is any value in Hz */
35#define CONFIG_CLKIN_HZ 25000000
36/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
37/* 1 = CLKIN / 2 */
38#define CONFIG_CLKIN_HALF 0
39/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
40/* 1 = bypass PLL */
41#define CONFIG_PLL_BYPASS 0
42/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
43/* Values can range from 0-63 (where 0 means 64) */
44#define CONFIG_VCO_MULT 20
45/* CCLK_DIV controls the core clock divider */
46/* Values can be 1, 2, 4, or 8 ONLY */
47#define CONFIG_CCLK_DIV 1
48/* SCLK_DIV controls the system clock divider */
49/* Values can range from 1-15 */
50#define CONFIG_SCLK_DIV 5
51
Mike Frysingerd7fdc142008-10-12 23:16:52 -040052/*
53 * Memory Settings
54 */
55#define CONFIG_MEM_SIZE 32
56#define CONFIG_MEM_ADD_WDTH 9
57
58#define CONFIG_EBIU_SDRRC_VAL 0x306
59#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
60
61#define CONFIG_EBIU_AMGCTL_VAL 0xFF
62#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
63#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
64
65#define CONFIG_SYS_MONITOR_LEN (256 << 10)
66#define CONFIG_SYS_MALLOC_LEN (128 << 10)
67
Mike Frysingerd7fdc142008-10-12 23:16:52 -040068/*
69 * Network Settings
70 */
71#ifndef __ADSPBF534__
72#define CONFIG_BFIN_MAC
73#define CONFIG_NETCONSOLE 1
Mike Frysingerd7fdc142008-10-12 23:16:52 -040074#endif
75#ifdef CONFIG_BFIN_MAC
76#define CONFIG_IPADDR 192.168.0.15
77#define CONFIG_NETMASK 255.255.255.0
78#define CONFIG_GATEWAYIP 192.168.0.1
79#define CONFIG_SERVERIP 192.168.0.2
80#define CONFIG_HOSTNAME bf537-minotaur
81#endif
82
83#define CONFIG_SYS_AUTOLOAD "no"
Joe Hershberger8b3637c2011-10-13 13:03:47 +000084#define CONFIG_ROOTPATH "/romfs"
Mike Frysingerd7fdc142008-10-12 23:16:52 -040085
Mike Frysingerd7fdc142008-10-12 23:16:52 -040086/*
87 * Flash Settings
88 */
89/* We don't have a parallel flash chip there */
90#define CONFIG_SYS_NO_FLASH
91
Mike Frysingerd7fdc142008-10-12 23:16:52 -040092/*
93 * SPI Settings
94 */
95#define CONFIG_BFIN_SPI
96#define CONFIG_ENV_SPI_MAX_HZ 30000000
Mike Frysingerafac8b02009-06-14 22:29:35 -040097#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingerd7fdc142008-10-12 23:16:52 -040098
Mike Frysingerd7fdc142008-10-12 23:16:52 -040099/*
100 * Env Storage Settings
101 */
102#define CONFIG_ENV_IS_IN_SPI_FLASH
103#define CONFIG_ENV_OFFSET 0x10000
104#define CONFIG_ENV_SIZE 0x10000
105#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger76d82182009-07-21 22:17:36 -0400106#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400107
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400108/*
109 * I2C settings
110 */
Scott Jiangc4697032014-11-13 15:30:55 +0800111#define CONFIG_SYS_I2C
Scott Jiangfea9b692014-11-13 15:30:53 +0800112#define CONFIG_SYS_I2C_ADI
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400113#define CONFIG_SYS_I2C_SPEED 50000
114#define CONFIG_SYS_I2C_SLAVE 0
115
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400116/*
117 * Misc Settings
118 */
119#define CONFIG_SYS_LONGHELP 1
120#define CONFIG_CMDLINE_EDITING 1
121#define CONFIG_ENV_OVERWRITE 1
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400122
123#define CONFIG_BAUDRATE 57600
124#define CONFIG_UART_CONSOLE 0
Sonic Zhang7a58eb92013-11-18 14:50:19 +0800125#define CONFIG_BFIN_SERIAL
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400126
127#define CONFIG_PANIC_HANG 1
128#define CONFIG_RTC_BFIN 1
129#define CONFIG_BOOT_RETRY_TIME -1
130#define CONFIG_LOADS_ECHO 1
131
132#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART)
133# define CONFIG_BOOTDELAY -1
134#else
135# define CONFIG_BOOTDELAY 5
136#endif
137
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400138#define CONFIG_CMD_BOOTLDR
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400139#define CONFIG_CMD_DATE
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400140
141#define CONFIG_BOOTCOMMAND "run ramboot"
142#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400143
144#define BOOT_ENV_SETTINGS \
145 "update=tftpboot $(loadaddr) u-boot.ldr;" \
Marek Vasut5368c552012-09-23 17:41:24 +0200146 "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400147 "sf erase 0 0x30000;" \
148 "sf write $(loadaddr) 0 $(filesize)" \
149 "flashboot=sf read 0x1000000 0x30000 0x320000;" \
150 "bootm 0x1000000\0"
151#ifdef CONFIG_BFIN_MAC
152# define NETWORK_ENV_SETTINGS \
153 "nfsargs=setenv bootargs root=/dev/nfs rw " \
154 "nfsroot=$(serverip):$(rootpath)\0" \
155 "addip=setenv bootargs $(bootargs) " \
156 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
157 ":$(hostname):eth0:off\0" \
158 "ramboot=tftpboot $(loadaddr) linux;" \
159 "run ramargs;run addip;bootelf\0" \
160 "nfsboot=tftpboot $(loadaddr) linux;" \
161 "run nfsargs;run addip;bootelf\0"
162#else
163# define NETWORK_ENV_SETTINGS
164#endif
165#define CONFIG_EXTRA_ENV_SETTINGS \
166 NETWORK_ENV_SETTINGS \
167 "ramargs=setenv bootargs " CONFIG_BOOTARGS "\0" \
168 BOOT_ENV_SETTINGS
169
Mike Frysingerd7fdc142008-10-12 23:16:52 -0400170#endif