Larry Johnson | c591dff | 2007-12-27 11:28:51 -0500 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Larry Johnson, lrj@acm.org |
| 4 | * |
| 5 | * (C) Copyright 2006 |
| 6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 7 | * |
| 8 | * (C) Copyright 2006 |
| 9 | * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com |
| 10 | * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #include <common.h> |
| 29 | #include <asm/processor.h> |
| 30 | #include <asm-ppc/io.h> |
| 31 | #include <i2c.h> |
| 32 | #include <ppc440.h> |
| 33 | |
| 34 | DECLARE_GLOBAL_DATA_PTR; |
| 35 | |
| 36 | extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
| 37 | |
| 38 | ulong flash_get_size(ulong base, int banknum); |
| 39 | |
| 40 | int board_early_init_f(void) |
| 41 | { |
| 42 | u32 sdr0_pfc1, sdr0_pfc2; |
| 43 | u32 gpio0_ir; |
| 44 | u32 reg; |
| 45 | int eth; |
| 46 | |
| 47 | mtdcr(ebccfga, xbcfg); |
| 48 | mtdcr(ebccfgd, 0xb8400000); |
| 49 | |
| 50 | /*-------------------------------------------------------------------- |
| 51 | * Setup the GPIO pins |
| 52 | * |
| 53 | * Korat GPIO usage: |
| 54 | * |
| 55 | * Init. |
| 56 | * Pin Source I/O value Function |
| 57 | * ------ ------ --- ----- --------------------------------- |
| 58 | * GPIO00 Alt1 I/O x PerAddr07 |
| 59 | * GPIO01 Alt1 I/O x PerAddr06 |
| 60 | * GPIO02 Alt1 I/O x PerAddr05 |
| 61 | * GPIO03 GPIO x x GPIO03 to expansion bus connector |
| 62 | * GPIO04 GPIO x x GPIO04 to expansion bus connector |
| 63 | * GPIO05 GPIO x x GPIO05 to expansion bus connector |
| 64 | * GPIO06 Alt1 O x PerCS1 (2nd NOR flash) |
| 65 | * GPIO07 Alt1 O x PerCS2 (CPLD) |
| 66 | * GPIO08 Alt1 O x PerCS3 to expansion bus connector |
| 67 | * GPIO09 Alt1 O x PerCS4 to expansion bus connector |
| 68 | * GPIO10 Alt1 O x PerCS5 to expansion bus connector |
| 69 | * GPIO11 Alt1 I x PerErr |
| 70 | * GPIO12 GPIO O 0 ATMega !Reset |
| 71 | * GPIO13 GPIO O 1 SPI Atmega !SS |
| 72 | * GPIO14 GPIO O 1 Write protect EEPROM #1 (0xA8) |
| 73 | * GPIO15 GPIO O 0 CPU Run LED !On |
| 74 | * GPIO16 Alt1 O x GMC1TxD0 |
| 75 | * GPIO17 Alt1 O x GMC1TxD1 |
| 76 | * GPIO18 Alt1 O x GMC1TxD2 |
| 77 | * GPIO19 Alt1 O x GMC1TxD3 |
| 78 | * GPIO20 Alt1 O x RejectPkt0 |
| 79 | * GPIO21 Alt1 O x RejectPkt1 |
| 80 | * GPIO22 GPIO I x PGOOD_DDR |
| 81 | * GPIO23 Alt1 O x SCPD0 |
| 82 | * GPIO24 Alt1 O x GMC0TxD2 |
| 83 | * GPIO25 Alt1 O x GMC0TxD3 |
| 84 | * GPIO26 GPIO? I/O x IIC0SDA (selected in SDR0_PFC4) |
| 85 | * GPIO27 GPIO O 0 PHY #0 1000BASE-X |
| 86 | * GPIO28 GPIO O 0 PHY #1 1000BASE-X |
| 87 | * GPIO29 GPIO I x Test jumper !Present |
| 88 | * GPIO30 GPIO I x SFP module #0 !Present |
| 89 | * GPIO31 GPIO I x SFP module #1 !Present |
| 90 | * |
| 91 | * GPIO32 GPIO O 1 SFP module #0 Tx !Enable |
| 92 | * GPIO33 GPIO O 1 SFP module #1 Tx !Enable |
| 93 | * GPIO34 Alt2 I x !UART1_CTS |
| 94 | * GPIO35 Alt2 O x !UART1_RTS |
| 95 | * GPIO36 Alt1 I x !UART0_CTS |
| 96 | * GPIO37 Alt1 O x !UART0_RTS |
| 97 | * GPIO38 Alt2 O x UART1_Tx |
| 98 | * GPIO39 Alt2 I x UART1_Rx |
| 99 | * GPIO40 Alt1 I x IRQ0 (Ethernet 0) |
| 100 | * GPIO41 Alt1 I x IRQ1 (Ethernet 1) |
| 101 | * GPIO42 Alt1 I x IRQ2 (PCI interrupt) |
| 102 | * GPIO43 Alt1 I x IRQ3 (System Alert from CPLD) |
| 103 | * GPIO44 xxxx x x (grounded through pulldown) |
| 104 | * GPIO45 GPIO O 0 PHY #0 Enable |
| 105 | * GPIO46 GPIO O 0 PHY #1 Enable |
| 106 | * GPIO47 GPIO I x Reset switch !Pressed |
| 107 | * GPIO48 GPIO I x Shutdown switch !Pressed |
| 108 | * GPIO49 xxxx x x (reserved for trace port) |
| 109 | * . . . . . |
| 110 | * . . . . . |
| 111 | * . . . . . |
| 112 | * GPIO63 xxxx x x (reserved for trace port) |
| 113 | *-------------------------------------------------------------------*/ |
| 114 | |
| 115 | out_be32((u32 *) GPIO0_OR, 0x00060000); |
| 116 | out_be32((u32 *) GPIO1_OR, 0xC0000000); |
| 117 | |
| 118 | out_be32((u32 *) GPIO0_OSRL, 0x54055400); |
| 119 | out_be32((u32 *) GPIO0_OSRH, 0x55015000); |
| 120 | out_be32((u32 *) GPIO1_OSRL, 0x02180000); |
| 121 | out_be32((u32 *) GPIO1_OSRH, 0x00000000); |
| 122 | |
| 123 | out_be32((u32 *) GPIO0_TSRL, 0x54055500); |
| 124 | out_be32((u32 *) GPIO0_TSRH, 0x00015000); |
| 125 | out_be32((u32 *) GPIO1_TSRL, 0x00000000); |
| 126 | out_be32((u32 *) GPIO1_TSRH, 0x00000000); |
| 127 | |
| 128 | out_be32((u32 *) GPIO0_TCR, 0x000FF0D8); |
| 129 | out_be32((u32 *) GPIO1_TCR, 0xD6060000); |
| 130 | |
| 131 | out_be32((u32 *) GPIO0_ISR1L, 0x54000100); |
| 132 | out_be32((u32 *) GPIO0_ISR1H, 0x00500000); |
| 133 | out_be32((u32 *) GPIO1_ISR1L, 0x00405500); |
| 134 | out_be32((u32 *) GPIO1_ISR1H, 0x00000000); |
| 135 | |
| 136 | out_be32((u32 *) GPIO0_ISR2L, 0x00000000); |
| 137 | out_be32((u32 *) GPIO0_ISR2H, 0x00000000); |
| 138 | out_be32((u32 *) GPIO1_ISR2L, 0x04010000); |
| 139 | out_be32((u32 *) GPIO1_ISR2H, 0x00000000); |
| 140 | |
| 141 | out_be32((u32 *) GPIO0_ISR3L, 0x00000000); |
| 142 | out_be32((u32 *) GPIO0_ISR3H, 0x00000000); |
| 143 | out_be32((u32 *) GPIO1_ISR3L, 0x00000000); |
| 144 | out_be32((u32 *) GPIO1_ISR3H, 0x00000000); |
| 145 | |
| 146 | /*-------------------------------------------------------------------- |
| 147 | * Setup the interrupt controller polarities, triggers, etc. |
| 148 | *-------------------------------------------------------------------*/ |
| 149 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
| 150 | mtdcr(uic0er, 0x00000000); /* disable all */ |
| 151 | mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */ |
| 152 | mtdcr(uic0pr, 0xfffff7ff); /* per ref-board manual */ |
| 153 | mtdcr(uic0tr, 0x00000000); /* per ref-board manual */ |
| 154 | mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */ |
| 155 | mtdcr(uic0sr, 0xffffffff); /* clear all */ |
| 156 | |
| 157 | mtdcr(uic1sr, 0xffffffff); /* clear all */ |
| 158 | mtdcr(uic1er, 0x00000000); /* disable all */ |
| 159 | mtdcr(uic1cr, 0x00000000); /* all non-critical */ |
| 160 | mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */ |
| 161 | mtdcr(uic1tr, 0x00000000); /* per ref-board manual */ |
| 162 | mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */ |
| 163 | mtdcr(uic1sr, 0xffffffff); /* clear all */ |
| 164 | |
| 165 | mtdcr(uic2sr, 0xffffffff); /* clear all */ |
| 166 | mtdcr(uic2er, 0x00000000); /* disable all */ |
| 167 | mtdcr(uic2cr, 0x00000000); /* all non-critical */ |
| 168 | mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */ |
| 169 | mtdcr(uic2tr, 0x00000000); /* per ref-board manual */ |
| 170 | mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */ |
| 171 | mtdcr(uic2sr, 0xffffffff); /* clear all */ |
| 172 | |
| 173 | /* take sim card reader and CF controller out of reset */ |
| 174 | out_8((u8 *) CFG_CPLD_BASE + 0x04, 0x80); |
| 175 | |
| 176 | /* Configure the two Ethernet PHYs. For each PHY, configure for fiber |
| 177 | * if the SFP module is present, and for copper if it is not present. |
| 178 | */ |
| 179 | gpio0_ir = in_be32((u32 *) GPIO0_IR); |
| 180 | for (eth = 0; eth < 2; ++eth) { |
| 181 | if (gpio0_ir & (0x00000001 << (1 - eth))) { |
| 182 | /* SFP module not present: configure PHY for copper. */ |
| 183 | /* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */ |
| 184 | out_8((u8 *) CFG_CPLD_BASE + 0x06, |
| 185 | in_8((u8 *) CFG_CPLD_BASE + 0x06) | |
| 186 | 0x06 << (4 * eth)); |
| 187 | } else { |
| 188 | /* SFP module present: configure PHY for fiber and |
| 189 | enable output */ |
| 190 | out_be32((u32 *) GPIO0_OR, in_be32((u32 *) GPIO0_OR) | |
| 191 | (0x00000001 << (4 - eth))); |
| 192 | out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) & |
| 193 | ~(0x00000001 << (31 - eth))); |
| 194 | } |
| 195 | } |
| 196 | /* enable Ethernet: set GPIO45 and GPIO46 to 1 */ |
| 197 | out_be32((u32 *) GPIO1_OR, in_be32((u32 *) GPIO1_OR) | 0x00060000); |
| 198 | |
| 199 | /* select Ethernet pins */ |
| 200 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
| 201 | sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | |
| 202 | SDR0_PFC1_SELECT_CONFIG_4; |
| 203 | mfsdr(SDR0_PFC2, sdr0_pfc2); |
| 204 | sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | |
| 205 | SDR0_PFC2_SELECT_CONFIG_4; |
| 206 | mtsdr(SDR0_PFC2, sdr0_pfc2); |
| 207 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
| 208 | |
| 209 | /* PCI arbiter enabled */ |
| 210 | mfsdr(sdr_pci0, reg); |
| 211 | mtsdr(sdr_pci0, 0x80000000 | reg); |
| 212 | |
| 213 | return 0; |
| 214 | } |
| 215 | |
| 216 | static int man_data_read(unsigned int addr) |
| 217 | { |
| 218 | /* |
| 219 | * Read an octet of data from address "addr" in the manufacturer's |
| 220 | * information serial EEPROM, or -1 on error. |
| 221 | */ |
| 222 | u8 data[2]; |
| 223 | |
| 224 | if (0 != i2c_probe(MAN_DATA_EEPROM_ADDR) || |
| 225 | 0 != i2c_read(MAN_DATA_EEPROM_ADDR, addr, 1, data, 1)) { |
| 226 | debug("man_data_read(0x%02X) failed\n", addr); |
| 227 | return -1; |
| 228 | } |
| 229 | debug("man_info_read(0x%02X) returned 0x%02X\n", addr, data[0]); |
| 230 | return data[0]; |
| 231 | } |
| 232 | |
| 233 | static unsigned int man_data_field_addr(unsigned int const field) |
| 234 | { |
| 235 | /* |
| 236 | * The manufacturer's information serial EEPROM contains a sequence of |
| 237 | * zero-delimited fields. Return the starting address of field "field", |
| 238 | * or 0 on error. |
| 239 | */ |
| 240 | unsigned addr, i; |
| 241 | |
| 242 | if (0 == field || 'A' != man_data_read(0) || '\0' != man_data_read(1)) |
| 243 | /* Only format "A" is currently supported */ |
| 244 | return 0; |
| 245 | |
| 246 | for (addr = 2, i = 1; i < field && addr < 256; ++addr) { |
| 247 | if ('\0' == man_data_read(addr)) |
| 248 | ++i; |
| 249 | } |
| 250 | return (addr < 256) ? addr : 0; |
| 251 | } |
| 252 | |
| 253 | static char *man_data_read_field(char s[], unsigned const field, |
| 254 | unsigned const length) |
| 255 | { |
| 256 | /* |
| 257 | * Place the null-terminated contents of field "field" of length |
| 258 | * "length" from the manufacturer's information serial EEPROM into |
| 259 | * string "s[length + 1]" and return a pointer to s, or return 0 on |
| 260 | * error. In either case the original contents of s[] is not preserved. |
| 261 | */ |
| 262 | unsigned addr, i; |
| 263 | |
| 264 | addr = man_data_field_addr(field); |
| 265 | if (0 == addr || addr + length >= 255) |
| 266 | return 0; |
| 267 | |
| 268 | for (i = 0; i < length; ++i) { |
| 269 | int const c = man_data_read(addr++); |
| 270 | |
| 271 | if (c <= 0) |
| 272 | return 0; |
| 273 | |
| 274 | s[i] = (char)c; |
| 275 | } |
| 276 | if (0 != man_data_read(addr)) |
| 277 | return 0; |
| 278 | |
| 279 | s[i] = '\0'; |
| 280 | return s; |
| 281 | } |
| 282 | |
| 283 | static void set_serial_number(void) |
| 284 | { |
| 285 | /* |
| 286 | * If the environmental variable "serial#" is not set, try to set it |
| 287 | * from the manufacturer's information serial EEPROM. |
| 288 | */ |
| 289 | char s[MAN_SERIAL_NO_LENGTH + 1]; |
| 290 | |
| 291 | if (0 == getenv("serial#") && |
| 292 | 0 != man_data_read_field(s, MAN_SERIAL_NO_FIELD, |
| 293 | MAN_SERIAL_NO_LENGTH)) |
| 294 | setenv("serial#", s); |
| 295 | } |
| 296 | |
| 297 | static void set_mac_addresses(void) |
| 298 | { |
| 299 | /* |
| 300 | * If the environmental variables "ethaddr" and/or "eth1addr" are not |
| 301 | * set, try to set them from the manufacturer's information serial |
| 302 | * EEPROM. |
| 303 | */ |
| 304 | char s[MAN_MAC_ADDR_LENGTH + 1]; |
| 305 | |
| 306 | if (0 != getenv("ethaddr") && 0 != getenv("eth1addr")) |
| 307 | return; |
| 308 | |
| 309 | if (0 == man_data_read_field(s, MAN_MAC_ADDR_FIELD, |
| 310 | MAN_MAC_ADDR_LENGTH)) |
| 311 | return; |
| 312 | |
| 313 | if (0 == getenv("ethaddr")) |
| 314 | setenv("ethaddr", s); |
| 315 | |
| 316 | if (0 == getenv("eth1addr")) { |
| 317 | ++s[MAN_MAC_ADDR_LENGTH - 1]; |
| 318 | setenv("eth1addr", s); |
| 319 | } |
| 320 | } |
| 321 | |
| 322 | /*---------------------------------------------------------------------------+ |
| 323 | | misc_init_r. |
| 324 | +---------------------------------------------------------------------------*/ |
| 325 | int misc_init_r(void) |
| 326 | { |
| 327 | uint pbcr; |
| 328 | int size_val = 0; |
| 329 | u32 reg; |
| 330 | unsigned long usb2d0cr = 0; |
| 331 | unsigned long usb2phy0cr, usb2h0cr = 0; |
| 332 | unsigned long sdr0_pfc1; |
| 333 | char *act = getenv("usbact"); |
| 334 | |
| 335 | /* |
| 336 | * FLASH stuff... |
| 337 | */ |
| 338 | |
| 339 | /* Re-do sizing to get full correct info */ |
| 340 | |
| 341 | /* adjust flash start and offset */ |
| 342 | gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; |
| 343 | gd->bd->bi_flashoffset = 0; |
| 344 | |
| 345 | mtdcr(ebccfga, pb0cr); |
| 346 | pbcr = mfdcr(ebccfgd); |
| 347 | switch (gd->bd->bi_flashsize) { |
| 348 | case 1 << 20: |
| 349 | size_val = 0; |
| 350 | break; |
| 351 | case 2 << 20: |
| 352 | size_val = 1; |
| 353 | break; |
| 354 | case 4 << 20: |
| 355 | size_val = 2; |
| 356 | break; |
| 357 | case 8 << 20: |
| 358 | size_val = 3; |
| 359 | break; |
| 360 | case 16 << 20: |
| 361 | size_val = 4; |
| 362 | break; |
| 363 | case 32 << 20: |
| 364 | size_val = 5; |
| 365 | break; |
| 366 | case 64 << 20: |
| 367 | size_val = 6; |
| 368 | break; |
| 369 | case 128 << 20: |
| 370 | size_val = 7; |
| 371 | break; |
| 372 | } |
| 373 | pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17); |
| 374 | mtdcr(ebccfga, pb0cr); |
| 375 | mtdcr(ebccfgd, pbcr); |
| 376 | |
| 377 | /* |
| 378 | * Re-check to get correct base address |
| 379 | */ |
| 380 | flash_get_size(gd->bd->bi_flashstart, 0); |
| 381 | |
| 382 | /* Monitor protection ON by default */ |
| 383 | (void)flash_protect(FLAG_PROTECT_SET, -CFG_MONITOR_LEN, 0xffffffff, |
| 384 | &flash_info[0]); |
| 385 | |
| 386 | /* Env protection ON by default */ |
| 387 | (void)flash_protect(FLAG_PROTECT_SET, |
| 388 | CFG_ENV_ADDR_REDUND, |
| 389 | CFG_ENV_ADDR_REDUND + 2 * CFG_ENV_SECT_SIZE - 1, |
| 390 | &flash_info[0]); |
| 391 | |
| 392 | /* |
| 393 | * USB suff... |
| 394 | */ |
| 395 | if (act == NULL || strcmp(act, "hostdev") == 0) { |
| 396 | /* SDR Setting */ |
| 397 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
| 398 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
| 399 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 400 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
| 401 | |
| 402 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; |
| 403 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ |
| 404 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; |
| 405 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1 */ |
| 406 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; |
| 407 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */ |
| 408 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; |
| 409 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */ |
| 410 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; |
| 411 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */ |
| 412 | |
| 413 | /* An 8-bit/60MHz interface is the only possible alternative |
| 414 | when connecting the Device to the PHY */ |
| 415 | usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; |
| 416 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1 */ |
| 417 | |
| 418 | /* To enable the USB 2.0 Device function through the UTMI interface */ |
| 419 | usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
| 420 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION; /*1 */ |
| 421 | |
| 422 | sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK; |
| 423 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0 */ |
| 424 | |
| 425 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
| 426 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
| 427 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 428 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
| 429 | |
| 430 | /*clear resets */ |
| 431 | udelay(1000); |
| 432 | mtsdr(SDR0_SRST1, 0x00000000); |
| 433 | udelay(1000); |
| 434 | mtsdr(SDR0_SRST0, 0x00000000); |
| 435 | |
| 436 | printf("USB: Host(int phy) Device(ext phy)\n"); |
| 437 | |
| 438 | } else if (strcmp(act, "dev") == 0) { |
| 439 | /*-------------------PATCH-------------------------------*/ |
| 440 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 441 | |
| 442 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; |
| 443 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ |
| 444 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; |
| 445 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0 */ |
| 446 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; |
| 447 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1 */ |
| 448 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; |
| 449 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1 */ |
| 450 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 451 | |
| 452 | udelay(1000); |
| 453 | mtsdr(SDR0_SRST1, 0x672c6000); |
| 454 | |
| 455 | udelay(1000); |
| 456 | mtsdr(SDR0_SRST0, 0x00000080); |
| 457 | |
| 458 | udelay(1000); |
| 459 | mtsdr(SDR0_SRST1, 0x60206000); |
| 460 | |
| 461 | *(unsigned int *)(0xe0000350) = 0x00000001; |
| 462 | |
| 463 | udelay(1000); |
| 464 | mtsdr(SDR0_SRST1, 0x60306000); |
| 465 | /*-------------------PATCH-------------------------------*/ |
| 466 | |
| 467 | /* SDR Setting */ |
| 468 | mfsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 469 | mfsdr(SDR0_USB2H0CR, usb2h0cr); |
| 470 | mfsdr(SDR0_USB2D0CR, usb2d0cr); |
| 471 | mfsdr(SDR0_PFC1, sdr0_pfc1); |
| 472 | |
| 473 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK; |
| 474 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0 */ |
| 475 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK; |
| 476 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ; /*0 */ |
| 477 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK; |
| 478 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1 */ |
| 479 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK; |
| 480 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV; /*0 */ |
| 481 | usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK; |
| 482 | usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV; /*0 */ |
| 483 | |
| 484 | usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK; |
| 485 | usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ; /*0 */ |
| 486 | |
| 487 | usb2d0cr = usb2d0cr & ~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK; |
| 488 | usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION; /*0 */ |
| 489 | |
| 490 | sdr0_pfc1 = sdr0_pfc1 & ~SDR0_PFC1_UES_MASK; |
| 491 | sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL; /*1 */ |
| 492 | |
| 493 | mtsdr(SDR0_USB2H0CR, usb2h0cr); |
| 494 | mtsdr(SDR0_USB2PHY0CR, usb2phy0cr); |
| 495 | mtsdr(SDR0_USB2D0CR, usb2d0cr); |
| 496 | mtsdr(SDR0_PFC1, sdr0_pfc1); |
| 497 | |
| 498 | /*clear resets */ |
| 499 | udelay(1000); |
| 500 | mtsdr(SDR0_SRST1, 0x00000000); |
| 501 | udelay(1000); |
| 502 | mtsdr(SDR0_SRST0, 0x00000000); |
| 503 | |
| 504 | printf("USB: Device(int phy)\n"); |
| 505 | } |
| 506 | |
| 507 | mfsdr(SDR0_SRST1, reg); /* enable security/kasumi engines */ |
| 508 | reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0); |
| 509 | mtsdr(SDR0_SRST1, reg); |
| 510 | |
| 511 | /* |
| 512 | * Clear PLB4A0_ACR[WRP] |
| 513 | * This fix will make the MAL burst disabling patch for the Linux |
| 514 | * EMAC driver obsolete. |
| 515 | */ |
| 516 | reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP; |
| 517 | mtdcr(plb4_acr, reg); |
| 518 | |
| 519 | set_serial_number(); |
| 520 | set_mac_addresses(); |
| 521 | return 0; |
| 522 | } |
| 523 | |
| 524 | int checkboard(void) |
| 525 | { |
| 526 | char const *const s = getenv("serial#"); |
| 527 | u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0); |
| 528 | u32 const gpio0_or = in_be32((u32 *) GPIO0_OR); |
| 529 | |
| 530 | printf("Board: Korat, Rev. %X", rev); |
| 531 | if (s != NULL) |
| 532 | printf(", serial# %s", s); |
| 533 | |
| 534 | printf(", Ethernet PHY 0: "); |
| 535 | if (gpio0_or & 0x00000010) |
| 536 | printf("fiber"); |
| 537 | else |
| 538 | printf("copper"); |
| 539 | |
| 540 | printf(", PHY 1: "); |
| 541 | if (gpio0_or & 0x00000008) |
| 542 | printf("fiber"); |
| 543 | else |
| 544 | printf("copper"); |
| 545 | |
| 546 | printf(".\n"); |
| 547 | return (0); |
| 548 | } |
| 549 | |
| 550 | #if defined(CFG_DRAM_TEST) |
| 551 | int testdram(void) |
| 552 | { |
| 553 | unsigned long *mem = (unsigned long *)0; |
| 554 | const unsigned long kend = (1024 / sizeof(unsigned long)); |
| 555 | unsigned long k, n; |
| 556 | |
| 557 | mtmsr(0); |
| 558 | |
| 559 | /* TODO: find correct size of SDRAM */ |
| 560 | for (k = 0; k < CFG_MBYTES_SDRAM; |
| 561 | ++k, mem += (1024 / sizeof(unsigned long))) { |
| 562 | if ((k & 1023) == 0) |
| 563 | printf("%3d MB\r", k / 1024); |
| 564 | |
| 565 | memset(mem, 0xaaaaaaaa, 1024); |
| 566 | for (n = 0; n < kend; ++n) { |
| 567 | if (mem[n] != 0xaaaaaaaa) { |
| 568 | printf("SDRAM test fails at: %08x\n", |
| 569 | (uint) & mem[n]); |
| 570 | return 1; |
| 571 | } |
| 572 | } |
| 573 | |
| 574 | memset(mem, 0x55555555, 1024); |
| 575 | for (n = 0; n < kend; ++n) { |
| 576 | if (mem[n] != 0x55555555) { |
| 577 | printf("SDRAM test fails at: %08x\n", |
| 578 | (uint) & mem[n]); |
| 579 | return 1; |
| 580 | } |
| 581 | } |
| 582 | } |
| 583 | printf("SDRAM test passes\n"); |
| 584 | return 0; |
| 585 | } |
| 586 | #endif /* defined(CFG_DRAM_TEST) */ |
| 587 | |
| 588 | /************************************************************************* |
| 589 | * pci_pre_init |
| 590 | * |
| 591 | * This routine is called just prior to registering the hose and gives |
| 592 | * the board the opportunity to check things. Returning a value of zero |
| 593 | * indicates that things are bad & PCI initialization should be aborted. |
| 594 | * |
| 595 | * Different boards may wish to customize the pci controller structure |
| 596 | * (add regions, override default access routines, etc) or perform |
| 597 | * certain pre-initialization actions. |
| 598 | * |
| 599 | ************************************************************************/ |
| 600 | #if defined(CONFIG_PCI) |
| 601 | int pci_pre_init(struct pci_controller *hose) |
| 602 | { |
| 603 | unsigned long addr; |
| 604 | |
| 605 | /*-------------------------------------------------------------------------+ |
| 606 | | Set priority for all PLB3 devices to 0. |
| 607 | | Set PLB3 arbiter to fair mode. |
| 608 | +-------------------------------------------------------------------------*/ |
| 609 | mfsdr(sdr_amp1, addr); |
| 610 | mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00); |
| 611 | addr = mfdcr(plb3_acr); |
| 612 | mtdcr(plb3_acr, addr | 0x80000000); |
| 613 | |
| 614 | /*-------------------------------------------------------------------------+ |
| 615 | | Set priority for all PLB4 devices to 0. |
| 616 | +-------------------------------------------------------------------------*/ |
| 617 | mfsdr(sdr_amp0, addr); |
| 618 | mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00); |
| 619 | addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */ |
| 620 | mtdcr(plb4_acr, addr); |
| 621 | |
| 622 | /*-------------------------------------------------------------------------+ |
| 623 | | Set Nebula PLB4 arbiter to fair mode. |
| 624 | +-------------------------------------------------------------------------*/ |
| 625 | /* Segment0 */ |
| 626 | addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair; |
| 627 | addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled; |
| 628 | addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; |
| 629 | addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep; |
| 630 | mtdcr(plb0_acr, addr); |
| 631 | |
| 632 | /* Segment1 */ |
| 633 | addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair; |
| 634 | addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled; |
| 635 | addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; |
| 636 | addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep; |
| 637 | mtdcr(plb1_acr, addr); |
| 638 | |
| 639 | return 1; |
| 640 | } |
| 641 | #endif /* defined(CONFIG_PCI) */ |
| 642 | |
| 643 | /************************************************************************* |
| 644 | * pci_target_init |
| 645 | * |
| 646 | * The bootstrap configuration provides default settings for the pci |
| 647 | * inbound map (PIM). But the bootstrap config choices are limited and |
| 648 | * may not be sufficient for a given board. |
| 649 | * |
| 650 | ************************************************************************/ |
| 651 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) |
| 652 | void pci_target_init(struct pci_controller *hose) |
| 653 | { |
| 654 | /*--------------------------------------------------------------------------+ |
| 655 | * Set up Direct MMIO registers |
| 656 | *--------------------------------------------------------------------------*/ |
| 657 | /*--------------------------------------------------------------------------+ |
| 658 | | PowerPC440EPX PCI Master configuration. |
| 659 | | Map one 1Gig range of PLB/processor addresses to PCI memory space. |
| 660 | | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF |
| 661 | | Use byte reversed out routines to handle endianess. |
| 662 | | Make this region non-prefetchable. |
| 663 | +--------------------------------------------------------------------------*/ |
| 664 | out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
| 665 | out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */ |
| 666 | out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */ |
| 667 | out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
| 668 | out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
| 669 | |
| 670 | out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ |
| 671 | out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */ |
| 672 | out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */ |
| 673 | out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ |
| 674 | out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ |
| 675 | |
| 676 | out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ |
| 677 | out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ |
| 678 | out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ |
| 679 | out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ |
| 680 | |
| 681 | /*--------------------------------------------------------------------------+ |
| 682 | * Set up Configuration registers |
| 683 | *--------------------------------------------------------------------------*/ |
| 684 | |
| 685 | /* Program the board's subsystem id/vendor id */ |
| 686 | pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, |
| 687 | CFG_PCI_SUBSYS_VENDORID); |
| 688 | pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID); |
| 689 | |
| 690 | /* Configure command register as bus master */ |
| 691 | pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); |
| 692 | |
| 693 | /* 240nS PCI clock */ |
| 694 | pci_write_config_word(0, PCI_LATENCY_TIMER, 1); |
| 695 | |
| 696 | /* No error reporting */ |
| 697 | pci_write_config_word(0, PCI_ERREN, 0); |
| 698 | |
| 699 | pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); |
| 700 | |
| 701 | /*--------------------------------------------------------------------------+ |
| 702 | * Set up Configuration registers for on-board NEC uPD720101 USB controller |
| 703 | *--------------------------------------------------------------------------*/ |
| 704 | pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020); |
| 705 | } |
| 706 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ |
| 707 | |
| 708 | /************************************************************************* |
| 709 | * pci_master_init |
| 710 | * |
| 711 | ************************************************************************/ |
| 712 | #if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) |
| 713 | void pci_master_init(struct pci_controller *hose) |
| 714 | { |
| 715 | unsigned short temp_short; |
| 716 | |
| 717 | /*--------------------------------------------------------------------------+ |
| 718 | | Write the PowerPC440 EP PCI Configuration regs. |
| 719 | | Enable PowerPC440 EP to be a master on the PCI bus (PMM). |
| 720 | | Enable PowerPC440 EP to act as a PCI memory target (PTM). |
| 721 | +--------------------------------------------------------------------------*/ |
| 722 | pci_read_config_word(0, PCI_COMMAND, &temp_short); |
| 723 | pci_write_config_word(0, PCI_COMMAND, |
| 724 | temp_short | PCI_COMMAND_MASTER | |
| 725 | PCI_COMMAND_MEMORY); |
| 726 | } |
| 727 | #endif |
| 728 | |
| 729 | /************************************************************************* |
| 730 | * is_pci_host |
| 731 | * |
| 732 | * This routine is called to determine if a pci scan should be |
| 733 | * performed. With various hardware environments (especially cPCI and |
| 734 | * PPMC) it's insufficient to depend on the state of the arbiter enable |
| 735 | * bit in the strap register, or generic host/adapter assumptions. |
| 736 | * |
| 737 | * Rather than hard-code a bad assumption in the general 440 code, the |
| 738 | * 440 pci code requires the board to decide at runtime. |
| 739 | * |
| 740 | * Return 0 for adapter mode, non-zero for host (monarch) mode. |
| 741 | * |
| 742 | * |
| 743 | ************************************************************************/ |
| 744 | #if defined(CONFIG_PCI) |
| 745 | int is_pci_host(struct pci_controller *hose) |
| 746 | { |
| 747 | /* Korat is always configured as host. */ |
| 748 | return (1); |
| 749 | } |
| 750 | #endif |
| 751 | |
| 752 | #if defined(CONFIG_POST) |
| 753 | /* |
| 754 | * Returns 1 if keys pressed to start the power-on long-running tests |
| 755 | * Called from board_init_f(). |
| 756 | */ |
| 757 | int post_hotkeys_pressed(void) |
| 758 | { |
| 759 | return 0; /* No hotkeys supported */ |
| 760 | } |
| 761 | #endif |