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Valentin Longchamp877bfe32013-10-18 11:47:24 +02001/*
2 * (C) Copyright 2013 Keymile AG
3 * Valentin Longchamp <valentin.longchamp@keymile.com>
4 *
5 * Copyright 2011,2012 Freescale Semiconductor, Inc.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <command.h>
12#include <netdev.h>
13#include <linux/compiler.h>
14#include <asm/mmu.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17#include <asm/immap_85xx.h>
18#include <asm/fsl_law.h>
19#include <asm/fsl_serdes.h>
20#include <asm/fsl_portals.h>
21#include <asm/fsl_liodn.h>
22#include <fm_eth.h>
23
24#include "../common/common.h"
25#include "kmp204x.h"
26
27DECLARE_GLOBAL_DATA_PTR;
28
29int checkboard(void)
30{
31 printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
32
33 return 0;
34}
35
Rainer Boschungf3e74d02014-02-03 08:45:40 +010036/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
37 * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
38 * For I2C only the low state is activly driven and high state is pulled-up
39 * by a resistor. Therefore the deblock GPIOs are used
40 * -> as an active output to drive a low state
41 * -> as an open-drain input to have a pulled-up high state
42 */
43
44/* QRIO GPIOs used for deblocking */
45#define DEBLOCK_PORT1 GPIO_A
46#define DEBLOCK_SCL1 20
47#define DEBLOCK_SDA1 21
48
49/* By default deblock GPIOs are floating */
50static void i2c_deblock_gpio_cfg(void)
Valentin Longchamp877bfe32013-10-18 11:47:24 +020051{
Rainer Boschungf3e74d02014-02-03 08:45:40 +010052 /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
53 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
54 qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
55
56 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
57 qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
Valentin Longchamp877bfe32013-10-18 11:47:24 +020058}
59
Rainer Boschungf3e74d02014-02-03 08:45:40 +010060void set_sda(int state)
61{
62 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
63}
64
65void set_scl(int state)
66{
67 qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
68}
69
70int get_sda(void)
71{
72 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
73}
74
75int get_scl(void)
76{
77 return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
78}
79
80
Valentin Longchamp877bfe32013-10-18 11:47:24 +020081#define ZL30158_RST 8
Valentin Longchampaf47faf2014-04-30 15:01:46 +020082#define BFTIC4_RST 0
Boschung, Rainera09f4702014-06-03 09:05:18 +020083#define RSTRQSR1_WDT_RR 0x00200000
84#define RSTRQSR1_SW_RR 0x00100000
Valentin Longchamp877bfe32013-10-18 11:47:24 +020085
86int board_early_init_f(void)
87{
88 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Boschung, Rainera09f4702014-06-03 09:05:18 +020089 bool cpuwd_flag = false;
Valentin Longchamp877bfe32013-10-18 11:47:24 +020090
Boschung, Rainere3917b22014-06-03 09:05:20 +020091 /* configure mode for uP reset request */
92 qrio_uprstreq(UPREQ_CORE_RST);
93
Valentin Longchamp877bfe32013-10-18 11:47:24 +020094 /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
95 setbits_be32(&gur->ddrclkdr, 0x001f000f);
96
Boschung, Rainera09f4702014-06-03 09:05:18 +020097 /* set reset reason according CPU register */
98 if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
99 RSTRQSR1_WDT_RR)
100 cpuwd_flag = true;
101
102 qrio_cpuwd_flag(cpuwd_flag);
103 /* clear CPU bits by writing 1 */
104 setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
105
Valentin Longchampaf47faf2014-04-30 15:01:46 +0200106 /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
107 qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
108 /* and enable WD on it */
109 qrio_wdmask(BFTIC4_RST, true);
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200110
Valentin Longchampf3839172014-08-19 15:40:04 +0200111 /* set the ZL30138's prstcfg to reset at power-up only */
112 qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
Valentin Longchampaf47faf2014-04-30 15:01:46 +0200113 /* and take it out of reset as soon as possible (needed for Hooper) */
114 qrio_prst(ZL30158_RST, false, false);
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200115
116 return 0;
117}
118
119int board_early_init_r(void)
120{
Valentin Longchamp27c78e02014-01-27 11:49:12 +0100121 int ret = 0;
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200122 /* Flush d-cache and invalidate i-cache of any FLASH data */
123 flush_dcache();
124 invalidate_icache();
125
126 set_liodns();
127 setup_portals();
128
Valentin Longchamp27c78e02014-01-27 11:49:12 +0100129 ret = trigger_fpga_config();
130 if (ret)
131 printf("error triggering PCIe FPGA config\n");
132
Stefan Biglera53e65d2014-05-02 10:48:41 +0200133 /* enable the Unit LED (red) & Boot LED (on) */
134 qrio_set_leds();
135
Stefan Bigler4921a142014-05-02 10:49:27 +0200136 /* enable Application Buffer */
137 qrio_enable_app_buffer();
138
Valentin Longchamp27c78e02014-01-27 11:49:12 +0100139 return ret;
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200140}
141
142unsigned long get_board_sys_clk(unsigned long dummy)
143{
144 return 66666666;
145}
146
Valentin Longchampaf47faf2014-04-30 15:01:46 +0200147#define ETH_FRONT_PHY_RST 15
148#define QSFP2_RST 11
149#define QSFP1_RST 10
150#define ZL30343_RST 9
151
Rainer Boschungf3e74d02014-02-03 08:45:40 +0100152int misc_init_f(void)
153{
154 /* configure QRIO pis for i2c deblocking */
155 i2c_deblock_gpio_cfg();
156
Valentin Longchampaf47faf2014-04-30 15:01:46 +0200157 /* configure the front phy's prstcfg and take it out of reset */
158 qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
159 qrio_prst(ETH_FRONT_PHY_RST, false, false);
160
Valentin Longchampf3839172014-08-19 15:40:04 +0200161 /* set the ZL30343 prstcfg to reset at power-up only */
162 qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
Valentin Longchampaf47faf2014-04-30 15:01:46 +0200163 /* and enable the WD on it */
164 qrio_wdmask(ZL30343_RST, true);
165
166 /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
167 qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
168 qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
169
170 /* and enable the WD on them */
171 qrio_wdmask(QSFP1_RST, true);
172 qrio_wdmask(QSFP2_RST, true);
173
Rainer Boschungf3e74d02014-02-03 08:45:40 +0100174 return 0;
175}
176
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200177#define NUM_SRDS_BANKS 2
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200178
179int misc_init_r(void)
180{
181 serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
182 u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
183 SRDS_PLLCR0_RFCK_SEL_125};
184 unsigned int i;
185
186 /* check SERDES reference clocks */
187 for (i = 0; i < NUM_SRDS_BANKS; i++) {
188 u32 actual = in_be32(&regs->bank[i].pllcr0);
189 actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
190 if (actual != expected[i]) {
191 printf("Warning: SERDES bank %u expects reference \
192 clock %sMHz, but actual is %sMHz\n", i + 1,
193 serdes_clock_to_string(expected[i]),
194 serdes_clock_to_string(actual));
195 }
196 }
197
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200198 return 0;
199}
200
201#if defined(CONFIG_HUSH_INIT_VAR)
202int hush_init_var(void)
203{
204 ivm_read_eeprom();
205 return 0;
206}
207#endif
208
209#if defined(CONFIG_LAST_STAGE_INIT)
Valentin Longchampaf47faf2014-04-30 15:01:46 +0200210
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200211int last_stage_init(void)
212{
Stefan Bigler4921a142014-05-02 10:49:27 +0200213#if defined(CONFIG_KMCOGE4)
214 /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
215 struct bfticu_iomap *bftic4 =
216 (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
217 u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
218
219 if (dip_switch != 0) {
220 /* start bootloader */
221 puts("DIP: Enabled\n");
222 setenv("actual_bank", "0");
223 }
224#endif
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200225 set_km_env();
Valentin Longchampaf47faf2014-04-30 15:01:46 +0200226
Valentin Longchamp877bfe32013-10-18 11:47:24 +0200227 return 0;
228}
229#endif
230
231#ifdef CONFIG_SYS_DPAA_FMAN
232void fdt_fixup_fman_mac_addresses(void *blob)
233{
234 int node, i, ret;
235 char *tmp, *end;
236 unsigned char mac_addr[6];
237
238 /* get the mac addr from env */
239 tmp = getenv("ethaddr");
240 if (!tmp) {
241 printf("ethaddr env variable not defined\n");
242 return;
243 }
244 for (i = 0; i < 6; i++) {
245 mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
246 if (tmp)
247 tmp = (*end) ? end+1 : end;
248 }
249
250 /* find the correct fdt ethernet path and correct it */
251 node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
252 if (node < 0) {
253 printf("no /soc/fman/ethernet path offset\n");
254 return;
255 }
256 ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
257 if (ret) {
258 printf("error setting local-mac-address property\n");
259 return;
260 }
261}
262#endif
263
264void ft_board_setup(void *blob, bd_t *bd)
265{
266 phys_addr_t base;
267 phys_size_t size;
268
269 ft_cpu_setup(blob, bd);
270
271 base = getenv_bootm_low();
272 size = getenv_bootm_size();
273
274 fdt_fixup_memory(blob, (u64)base, (u64)size);
275
276#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
277 fdt_fixup_dr_usb(blob, bd);
278#endif
279
280#ifdef CONFIG_PCI
281 pci_of_setup(blob, bd);
282#endif
283
284 fdt_fixup_liodn(blob);
285#ifdef CONFIG_SYS_DPAA_FMAN
286 fdt_fixup_fman_ethernet(blob);
287 fdt_fixup_fman_mac_addresses(blob);
288#endif
289}
Valentin Longchamp18794942014-04-30 15:01:44 +0200290
291#if defined(CONFIG_POST)
292
293/* DIC26_SELFTEST GPIO used to start factory test sw */
294#define SELFTEST_PORT GPIO_A
295#define SELFTEST_PIN 31
296
297int post_hotkeys_pressed(void)
298{
299 qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
300 return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
301}
302#endif