| Vignesh Raghavendra | 53b04c6 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com |
| 4 | */ |
| 5 | |
| 6 | #ifndef K3_PSIL_H_ |
| 7 | #define K3_PSIL_H_ |
| 8 | |
| 9 | #include <linux/types.h> |
| 10 | |
| 11 | #define K3_PSIL_DST_THREAD_ID_OFFSET 0x8000 |
| 12 | |
| 13 | struct device; |
| 14 | |
| 15 | /** |
| 16 | * enum udma_tp_level - Channel Throughput Levels |
| 17 | * @UDMA_TP_NORMAL: Normal channel |
| 18 | * @UDMA_TP_HIGH: High Throughput channel |
| 19 | * @UDMA_TP_ULTRAHIGH: Ultra High Throughput channel |
| 20 | */ |
| 21 | enum udma_tp_level { |
| 22 | UDMA_TP_NORMAL = 0, |
| 23 | UDMA_TP_HIGH, |
| 24 | UDMA_TP_ULTRAHIGH, |
| 25 | UDMA_TP_LAST, |
| 26 | }; |
| 27 | |
| 28 | /** |
| 29 | * enum psil_endpoint_type - PSI-L Endpoint type |
| 30 | * @PSIL_EP_NATIVE: Normal channel |
| 31 | * @PSIL_EP_PDMA_XY: XY mode PDMA |
| 32 | * @PSIL_EP_PDMA_MCAN: MCAN mode PDMA |
| 33 | * @PSIL_EP_PDMA_AASRC: AASRC mode PDMA |
| 34 | */ |
| 35 | enum psil_endpoint_type { |
| 36 | PSIL_EP_NATIVE = 0, |
| 37 | PSIL_EP_PDMA_XY, |
| 38 | PSIL_EP_PDMA_MCAN, |
| 39 | PSIL_EP_PDMA_AASRC, |
| 40 | }; |
| 41 | |
| 42 | /** |
| 43 | * struct psil_endpoint_config - PSI-L Endpoint configuration |
| 44 | * @ep_type: PSI-L endpoint type |
| 45 | * @pkt_mode: If set, the channel must be in Packet mode, otherwise in |
| 46 | * TR mode |
| 47 | * @notdpkt: TDCM must be suppressed on the TX channel |
| 48 | * @needs_epib: Endpoint needs EPIB |
| 49 | * @psd_size: If set, PSdata is used by the endpoint |
| 50 | * @channel_tpl: Desired throughput level for the channel |
| 51 | * @pdma_acc32: ACC32 must be enabled on the PDMA side |
| 52 | * @pdma_burst: BURST must be enabled on the PDMA side |
| 53 | */ |
| 54 | struct psil_endpoint_config { |
| 55 | enum psil_endpoint_type ep_type; |
| 56 | |
| 57 | unsigned pkt_mode:1; |
| 58 | unsigned notdpkt:1; |
| 59 | unsigned needs_epib:1; |
| 60 | u32 psd_size; |
| 61 | enum udma_tp_level channel_tpl; |
| 62 | |
| 63 | /* PDMA properties, valid for PSIL_EP_PDMA_* */ |
| 64 | unsigned pdma_acc32:1; |
| 65 | unsigned pdma_burst:1; |
| 66 | }; |
| 67 | #endif /* K3_PSIL_H_ */ |