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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocherc0dcece2013-08-19 16:39:01 +02002/*
3 * siemens rut
4 * (C) Copyright 2013 Siemens Schweiz AG
5 * (C) Heiko Schocher, DENX Software Engineering, hs@denx.de.
6 *
7 * Based on:
8 * U-Boot file:/include/configs/am335x_evm.h
9 *
10 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
Heiko Schocherc0dcece2013-08-19 16:39:01 +020011 */
12
13#ifndef __CONFIG_RUT_H
14#define __CONFIG_RUT_H
15
Heiko Schocherc0dcece2013-08-19 16:39:01 +020016#define CONFIG_SIEMENS_MACH_TYPE MACH_TYPE_RUT
17
18#include "siemens-am33x-common.h"
19
Heiko Schocherc0dcece2013-08-19 16:39:01 +020020#define RUT_IOCTRL_VAL 0x18b
21#define DDR_PLL_FREQ 303
22
23 /* Physical Memory Map */
24#define CONFIG_MAX_RAM_BANK_SIZE (256 << 20) /* 256 MiB */
25
26/* I2C Configuration */
27#define CONFIG_SYS_I2C_SPEED 100000
28
29#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
30#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
31#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
32#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
33
Heiko Schocherc0dcece2013-08-19 16:39:01 +020034#define CONFIG_PHY_NATSEMI
35
36#define CONFIG_FACTORYSET
37
Heiko Schocherc0dcece2013-08-19 16:39:01 +020038/* Watchdog */
39#define WATCHDOG_TRIGGER_GPIO 14
40
41#ifndef CONFIG_SPL_BUILD
42
Heiko Schocher61159b72015-06-16 14:59:34 +020043/* Use common default */
Heiko Schocher61159b72015-06-16 14:59:34 +020044
Heiko Schocherc0dcece2013-08-19 16:39:01 +020045/* Default env settings */
46#define CONFIG_EXTRA_ENV_SETTINGS \
47 "hostname=rut\0" \
Heiko Schocher6b3943f2016-06-07 08:55:45 +020048 "ubi_off=2048\0"\
Samuel Egli56eb3da2013-11-04 14:05:03 +010049 "nand_img_size=0x500000\0" \
50 "splashpos=m,m\0" \
Heiko Schocherc0dcece2013-08-19 16:39:01 +020051 "optargs=fixrtc --no-log consoleblank=0 \0" \
Heiko Schocher61159b72015-06-16 14:59:34 +020052 CONFIG_ENV_SETTINGS_V1 \
53 CONFIG_ENV_SETTINGS_NAND_V1 \
Heiko Schocherc0dcece2013-08-19 16:39:01 +020054 "mmc_dev=0\0" \
55 "mmc_root=/dev/mmcblk0p2 rw\0" \
56 "mmc_root_fs_type=ext4 rootwait\0" \
57 "mmc_load_uimage=" \
58 "mmc rescan; " \
59 "setenv bootfile uImage;" \
60 "fatload mmc ${mmc_dev} ${kloadaddr} ${bootfile}\0" \
61 "loadbootenv=fatload mmc ${mmc_dev} ${loadaddr} ${bootenv}\0" \
62 "importbootenv=echo Importing environment from mmc ...; " \
63 "env import -t $loadaddr $filesize\0" \
64 "mmc_args=run bootargs_defaults;" \
65 "mtdparts default;" \
66 "setenv bootargs ${bootargs} " \
67 "root=${mmc_root} ${mtdparts}" \
68 "rootfstype=${mmc_root_fs_type} ip=${ip_method} " \
69 "eth=${ethaddr} " \
70 "\0" \
71 "mmc_boot=run mmc_args; " \
72 "run mmc_load_uimage; " \
73 "bootm ${kloadaddr}\0" \
74 ""
75
76#ifndef CONFIG_RESTORE_FLASH
77/* set to negative value for no autoboot */
Heiko Schocherc0dcece2013-08-19 16:39:01 +020078
79#define CONFIG_BOOTCOMMAND \
80 "if mmc rescan; then " \
81 "echo SD/MMC found on device ${mmc_dev};" \
82 "if run loadbootenv; then " \
83 "echo Loaded environment from ${bootenv};" \
84 "run importbootenv;" \
85 "fi;" \
86 "if test -n $uenvcmd; then " \
87 "echo Running uenvcmd ...;" \
88 "run uenvcmd;" \
89 "fi;" \
90 "if run mmc_load_uimage; then " \
91 "run mmc_args;" \
92 "bootm ${kloadaddr};" \
93 "fi;" \
94 "fi;" \
95 "run nand_boot;" \
Samuel Egli56eb3da2013-11-04 14:05:03 +010096 "reset;"
Heiko Schocherc0dcece2013-08-19 16:39:01 +020097
98#else
Heiko Schocherc0dcece2013-08-19 16:39:01 +020099
100#define CONFIG_BOOTCOMMAND \
101 "setenv autoload no; " \
102 "dhcp; " \
103 "if tftp 80000000 debrick.scr; then " \
104 "source 80000000; " \
105 "fi"
106#endif
107
108#endif /* CONFIG_SPL_BUILD */
109
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200110#if defined(CONFIG_VIDEO)
111#define CONFIG_VIDEO_DA8XX
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200112#define CONFIG_SPLASH_SCREEN
113#define CONFIG_SPLASH_SCREEN_ALIGN
114#define CONFIG_VIDEO_LOGO
115#define CONFIG_VIDEO_BMP_RLE8
116#define CONFIG_VIDEO_BMP_LOGO
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200117#define DA8XX_LCD_CNTL_BASE LCD_CNTL_BASE
118
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200119#define BOARD_LCD_RESET 115 /* Bank 3 pin 19 */
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200120#define CONFIG_FORMIKE
Samuel Egli56eb3da2013-11-04 14:05:03 +0100121#define DISPL_PLL_SPREAD_SPECTRUM
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200122#endif
123
Heiko Schocherc0dcece2013-08-19 16:39:01 +0200124#endif /* ! __CONFIG_RUT_H */