| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| Jimmy Zhang | c5b34a2 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2011 The Chromium OS Authors. |
| Jimmy Zhang | c5b34a2 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 7 | #include <asm/global_data.h> |
| Jeroen Hofstee | 19d7bf3 | 2014-10-08 22:57:46 +0200 | [diff] [blame] | 8 | #include "emc.h" |
| Jimmy Zhang | c5b34a2 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 9 | #include <asm/io.h> |
| Jimmy Zhang | c5b34a2 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 10 | #include <asm/arch/clock.h> |
| 11 | #include <asm/arch/emc.h> |
| Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 12 | #include <asm/arch/tegra.h> |
| 13 | #include <asm/arch-tegra/ap.h> |
| 14 | #include <asm/arch-tegra/clk_rst.h> |
| Thierry Reding | e9c58f2 | 2019-04-15 11:32:17 +0200 | [diff] [blame] | 15 | #include <asm/arch-tegra/pmu.h> |
| Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 16 | #include <asm/arch-tegra/sys_proto.h> |
| Jimmy Zhang | c5b34a2 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | /* These rates are hard-coded for now, until fdt provides them */ |
| 21 | #define EMC_SDRAM_RATE_T20 (333000 * 2 * 1000) |
| 22 | #define EMC_SDRAM_RATE_T25 (380000 * 2 * 1000) |
| 23 | |
| 24 | int board_emc_init(void) |
| 25 | { |
| 26 | unsigned rate; |
| 27 | |
| Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 28 | switch (tegra_get_chip_sku()) { |
| Jimmy Zhang | c5b34a2 | 2012-04-10 05:17:06 +0000 | [diff] [blame] | 29 | default: |
| 30 | case TEGRA_SOC_T20: |
| 31 | rate = EMC_SDRAM_RATE_T20; |
| 32 | break; |
| 33 | case TEGRA_SOC_T25: |
| 34 | rate = EMC_SDRAM_RATE_T25; |
| 35 | break; |
| 36 | } |
| 37 | return tegra_set_emc(gd->fdt_blob, rate); |
| 38 | } |