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Wolfgang Denk8cba0902006-05-12 16:15:46 +02001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_VIRTLAB2 1 /* ...on a virtlab2 module */
38#define CONFIG_TQM8xxL 1
39
40#ifdef CONFIG_LCD /* with LCD controller ? */
41#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
42#endif
43
44#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
48
49#define CONFIG_BOOTCOUNT_LIMIT
50
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52
53#define CONFIG_BOARD_TYPES 1 /* support board types */
54
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010055#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
Wolfgang Denk8cba0902006-05-12 16:15:46 +020056
57#undef CONFIG_BOOTARGS
58
59#define CONFIG_EXTRA_ENV_SETTINGS \
60 "netdev=eth0\0" \
61 "nfsargs=setenv bootargs root=/dev/nfs rw " \
62 "nfsroot=${serverip}:${rootpath}\0" \
63 "ramargs=setenv bootargs root=/dev/ram rw\0" \
64 "addip=setenv bootargs ${bootargs} " \
65 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
66 ":${hostname}:${netdev}:off panic=1\0" \
67 "flash_nfs=run nfsargs addip;" \
68 "bootm ${kernel_addr}\0" \
69 "flash_self=run ramargs addip;" \
70 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
71 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
72 "rootpath=/opt/eldk/ppc_8xx\0" \
73 "bootfile=/tftpboot/TQM823L/uImage\0" \
74 "kernel_addr=40040000\0" \
75 "ramdisk_addr=40100000\0" \
76 ""
77#define CONFIG_BOOTCOMMAND "run flash_self"
78
79#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
80#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
81
82#undef CONFIG_WATCHDOG /* watchdog disabled */
83
84#if defined(CONFIG_LCD)
85# undef CONFIG_STATUS_LED /* disturbs display */
86#else
87# define CONFIG_STATUS_LED 1 /* Status LED enabled */
88#endif /* CONFIG_LCD */
89
90#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
91
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -050092/*
93 * BOOTP options
94 */
95#define CONFIG_BOOTP_SUBNETMASK
96#define CONFIG_BOOTP_GATEWAY
97#define CONFIG_BOOTP_HOSTNAME
98#define CONFIG_BOOTP_BOOTPATH
99#define CONFIG_BOOTP_BOOTFILESIZE
100
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200101
102#define CONFIG_MAC_PARTITION
103#define CONFIG_DOS_PARTITION
104
105#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
106
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500107
108/*
109 * Command line configuration.
110 */
111#include <config_cmd_default.h>
112
113#define CONFIG_CMD_ASKENV
114#define CONFIG_CMD_DATE
115#define CONFIG_CMD_DHCP
116#define CONFIG_CMD_IDE
117#define CONFIG_CMD_NFS
118#define CONFIG_CMD_SNTP
119
120#if defined(CONFIG_SPLASH_SCREEN)
121 #define CONFIG_CMD_BMP
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200122#endif
123
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200124
125/*
126 * Miscellaneous configurable options
127 */
128#define CFG_LONGHELP /* undef to save memory */
129#define CFG_PROMPT "=> " /* Monitor Command Prompt */
130
131#if 0
132#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
133#endif
134#ifdef CFG_HUSH_PARSER
135#define CFG_PROMPT_HUSH_PS2 "> "
136#endif
137
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500138#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200139#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
140#else
141#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
142#endif
143#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
144#define CFG_MAXARGS 16 /* max number of command args */
145#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
146
147#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
148#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
149
150#define CFG_LOAD_ADDR 0x100000 /* default load address */
151
152#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
153
154#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
155
156/*
157 * Low Level Configuration Settings
158 * (address mappings, register initial values, etc.)
159 * You should know what you are doing if you make changes here.
160 */
161/*-----------------------------------------------------------------------
162 * Internal Memory Mapped Register
163 */
164#define CFG_IMMR 0xFFF00000
165
166/*-----------------------------------------------------------------------
167 * Definitions for initial stack pointer and data area (in DPRAM)
168 */
169#define CFG_INIT_RAM_ADDR CFG_IMMR
170#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
171#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
172#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
173#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
174
175/*-----------------------------------------------------------------------
176 * Start addresses for the final memory configuration
177 * (Set up by the startup code)
178 * Please note that CFG_SDRAM_BASE _must_ start at 0
179 */
180#define CFG_SDRAM_BASE 0x00000000
181#define CFG_FLASH_BASE 0x40000000
182#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
183#define CFG_MONITOR_BASE CFG_FLASH_BASE
184#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
185
186/*
187 * For booting Linux, the board info and command line data
188 * have to be in the first 8 MB of memory, since this is
189 * the maximum mapped by the Linux kernel during initialization.
190 */
191#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
192
193/*-----------------------------------------------------------------------
194 * FLASH organization
195 */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200196
Martin Krausee318d9e2007-09-27 11:10:08 +0200197/* use CFI flash driver */
198#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
199#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
200#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
201#define CFG_FLASH_EMPTY_INFO
202#define CFG_FLASH_USE_BUFFER_WRITE 1
203#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
204#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200205
206#define CFG_ENV_IS_IN_FLASH 1
207#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
208#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
209
210/* Address and size of Redundant Environment Sector */
211#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
212#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
213
Wolfgang Denk67c31032007-09-16 17:10:04 +0200214#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
215
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200216/*-----------------------------------------------------------------------
217 * Hardware Information Block
218 */
219#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
220#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
221#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
222
223/*-----------------------------------------------------------------------
224 * Cache Configuration
225 */
226#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500227#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200228#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
229#endif
230
231/*-----------------------------------------------------------------------
232 * SYPCR - System Protection Control 11-9
233 * SYPCR can only be written once after reset!
234 *-----------------------------------------------------------------------
235 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
236 */
237#if defined(CONFIG_WATCHDOG)
238#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
239 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
240#else
241#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
242#endif
243
244/*-----------------------------------------------------------------------
245 * SIUMCR - SIU Module Configuration 11-6
246 *-----------------------------------------------------------------------
247 * PCMCIA config., multi-function pin tri-state
248 */
249#ifndef CONFIG_CAN_DRIVER
250#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
251#else /* we must activate GPL5 in the SIUMCR for CAN */
252#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
253#endif /* CONFIG_CAN_DRIVER */
254
255/*-----------------------------------------------------------------------
256 * TBSCR - Time Base Status and Control 11-26
257 *-----------------------------------------------------------------------
258 * Clear Reference Interrupt Status, Timebase freezing enabled
259 */
260#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
261
262/*-----------------------------------------------------------------------
263 * RTCSC - Real-Time Clock Status and Control Register 11-27
264 *-----------------------------------------------------------------------
265 */
266#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
267
268/*-----------------------------------------------------------------------
269 * PISCR - Periodic Interrupt Status and Control 11-31
270 *-----------------------------------------------------------------------
271 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
272 */
273#define CFG_PISCR (PISCR_PS | PISCR_PITF)
274
275/*-----------------------------------------------------------------------
276 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
277 *-----------------------------------------------------------------------
278 * Reset PLL lock status sticky bit, timer expired status bit and timer
279 * interrupt status bit
280 */
281#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
282
283/*-----------------------------------------------------------------------
284 * SCCR - System Clock and reset Control Register 15-27
285 *-----------------------------------------------------------------------
286 * Set clock output, timebase and RTC source and divider,
287 * power management and some other internal clocks
288 */
289#define SCCR_MASK SCCR_EBDF11
290#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
291 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
292 SCCR_DFALCD00)
293
294/*-----------------------------------------------------------------------
295 * PCMCIA stuff
296 *-----------------------------------------------------------------------
297 *
298 */
299#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
300#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
301#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
302#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
303#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
304#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
305#define CFG_PCMCIA_IO_ADDR (0xEC000000)
306#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
307
308/*-----------------------------------------------------------------------
309 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
310 *-----------------------------------------------------------------------
311 */
312
313#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
314
315#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
316#undef CONFIG_IDE_LED /* LED for ide not supported */
317#undef CONFIG_IDE_RESET /* reset for ide not supported */
318
319#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
320#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
321
322#define CFG_ATA_IDE0_OFFSET 0x0000
323
324#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
325
326/* Offset for data I/O */
327#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
328
329/* Offset for normal register accesses */
330#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
331
332/* Offset for alternate registers */
333#define CFG_ATA_ALT_OFFSET 0x0100
334
335/*-----------------------------------------------------------------------
336 *
337 *-----------------------------------------------------------------------
338 *
339 */
340#define CFG_DER 0
341
342/*
343 * Init Memory Controller:
344 *
345 * BR0/1 and OR0/1 (FLASH)
346 */
347
348#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
349#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
350
351/* used to re-map FLASH both when starting from SRAM or FLASH:
352 * restrict access enough to keep SRAM working (if any)
353 * but not too much to meddle with FLASH accesses
354 */
355#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
356#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
357
358/*
359 * FLASH timing:
360 */
361#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
362 OR_SCY_3_CLK | OR_EHTR | OR_BI)
363
364#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
365#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
366#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
367
368#define CFG_OR1_REMAP CFG_OR0_REMAP
369#define CFG_OR1_PRELIM CFG_OR0_PRELIM
370#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
371
372/*
373 * BR2/3 and OR2/3 (SDRAM)
374 *
375 */
376#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
377#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
378#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
379
380/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
381#define CFG_OR_TIMING_SDRAM 0x00000A00
382
383#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
384#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
385
386#ifndef CONFIG_CAN_DRIVER
387#define CFG_OR3_PRELIM CFG_OR2_PRELIM
388#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
389#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
390#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
391#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
392#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
393#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
394 BR_PS_8 | BR_MS_UPMB | BR_V )
395#endif /* CONFIG_CAN_DRIVER */
396
397/*
398 * Memory Periodic Timer Prescaler
399 *
400 * The Divider for PTA (refresh timer) configuration is based on an
401 * example SDRAM configuration (64 MBit, one bank). The adjustment to
402 * the number of chip selects (NCS) and the actually needed refresh
403 * rate is done by setting MPTPR.
404 *
405 * PTA is calculated from
406 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
407 *
408 * gclk CPU clock (not bus clock!)
409 * Trefresh Refresh cycle * 4 (four word bursts used)
410 *
411 * 4096 Rows from SDRAM example configuration
412 * 1000 factor s -> ms
413 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
414 * 4 Number of refresh cycles per period
415 * 64 Refresh cycle in ms per number of rows
416 * --------------------------------------------
417 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
418 *
419 * 50 MHz => 50.000.000 / Divider = 98
420 * 66 Mhz => 66.000.000 / Divider = 129
421 * 80 Mhz => 80.000.000 / Divider = 156
422 */
423
424#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
425#define CFG_MAMR_PTA 98
426
427/*
428 * For 16 MBit, refresh rates could be 31.3 us
429 * (= 64 ms / 2K = 125 / quad bursts).
430 * For a simpler initialization, 15.6 us is used instead.
431 *
432 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
433 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
434 */
435#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
436#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
437
438/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
439#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
440#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
441
442/*
443 * MAMR settings for SDRAM
444 */
445
446/* 8 column SDRAM */
447#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
448 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
449 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
450/* 9 column SDRAM */
451#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
452 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
453 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
454
455
456/*
457 * Internal Definitions
458 *
459 * Boot Flags
460 */
461#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
462#define BOOTFLAG_WARM 0x02 /* Software reboot */
463
464/* Map peripheral control registers on CS4 */
465#define CFG_PERIPHERAL_BASE 0xA0000000
466#define CFG_PERIPHERAL_OR_AM 0xFFFF8000 /* 32 kB address mask */
467#define CFG_OR4_PRELIM (CFG_PERIPHERAL_OR_AM | OR_TRLX | OR_CSNT_SAM | \
468 OR_SCY_2_CLK)
469#define CFG_BR4_PRELIM ((CFG_PERIPHERAL_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
470#define PCMCIA_CTRL (CFG_PERIPHERAL_BASE + 0xB00)
471#endif /* __CONFIG_H */