blob: 4147b45ef0eb81dd604163f388b8bc25d39500e8 [file] [log] [blame]
Tom McLeod413ab5b2017-09-27 17:53:26 -07001/*
2 * (C) Copyright 2012 Xilinx
3 * (C) Copyright 2017 Opal Kelly Inc.
4 *
5 * Configuration settings for the SYZYGY Hub development board
6 * See zynq-common.h for Zynq common configs
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#ifndef __CONFIG_SYZYGY_HUB_H
12#define __CONFIG_SYZYGY_HUB_H
13
14#define CONFIG_ZYNQ_I2C1
15#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
16#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x57
17#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0xFA
18
19#define CONFIG_EXTRA_ENV_SETTINGS \
20 "fit_image=fit.itb\0" \
21 "bitstream_image=download.bit\0" \
22 "loadbit_addr=0x1000000\0" \
23 "load_addr=0x2000000\0" \
24 "fit_size=0x800000\0" \
25 "flash_off=0x100000\0" \
26 "nor_flash_off=0xE2100000\0" \
27 "fdt_high=0x20000000\0" \
28 "initrd_high=0x20000000\0" \
29 "loadbootenv_addr=0x2000000\0" \
30 "fdt_addr_r=0x1f00000\0" \
31 "pxefile_addr_r=0x2000000\0" \
32 "kernel_addr_r=0x2000000\0" \
33 "scriptaddr=0x3000000\0" \
34 "ramdisk_addr_r=0x3100000\0" \
35 "bootenv=uEnv.txt\0" \
36 "bootenv_dev=mmc\0" \
37 "loadbootenv=load ${bootenv_dev} 0 ${loadbootenv_addr} ${bootenv}\0" \
38 "importbootenv=echo Importing environment from ${bootenv_dev} ...; " \
39 "env import -t ${loadbootenv_addr} $filesize\0" \
40 "bootenv_existence_test=test -e ${bootenv_dev} 0 /${bootenv}\0" \
41 "setbootenv=if env run bootenv_existence_test; then " \
42 "if env run loadbootenv; then " \
43 "env run importbootenv; " \
44 "fi; " \
45 "fi; \0" \
46 "sd_loadbootenv=set bootenv_dev mmc && " \
47 "run setbootenv \0" \
48 "usb_loadbootenv=set bootenv_dev usb && usb start && run setbootenv\0" \
49 "preboot=if test $modeboot = sdboot; then " \
50 "run sd_loadbootenv; " \
51 "echo Checking if uenvcmd is set ...; " \
52 "if test -n $uenvcmd; then " \
53 "echo Running uenvcmd ...; " \
54 "run uenvcmd; " \
55 "fi; " \
56 "fi; \0" \
57 "sdboot=echo Copying FPGA Bitstream from SD to RAM... && " \
58 "load mmc 0 ${loadbit_addr} ${bitstream_image} && " \
59 "echo Programming FPGA... && " \
60 "fpga loadb 0 ${loadbit_addr} ${filesize} && " \
61 "echo Copying FIT from SD to RAM... && " \
62 "load mmc 0 ${load_addr} ${fit_image} && " \
63 "bootm ${load_addr}\0" \
64 "jtagboot=echo TFTPing FIT to RAM... && " \
65 "tftpboot ${load_addr} ${fit_image} && " \
66 "bootm ${load_addr}\0" \
67 DFU_ALT_INFO \
68 BOOTENV
69
70#include <configs/zynq-common.h>
71
72#endif /* __CONFIG_SYZYGY_HUB_H */