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Michal Simekbaba22a2022-05-18 12:49:26 +02001// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for KR260 revA Carrier Card
4 *
5 * (C) Copyright 2021, Xilinx, Inc.
6 *
Michal Simek174d72842023-07-10 14:35:49 +02007 * Michal Simek <michal.simek@amd.com>
Michal Simekbaba22a2022-05-18 12:49:26 +02008 */
9
10#include <dt-bindings/gpio/gpio.h>
11#include <dt-bindings/net/ti-dp83867.h>
12#include <dt-bindings/phy/phy.h>
13#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
14
15/dts-v1/;
16/plugin/;
17
18&{/} {
19 compatible = "xlnx,zynqmp-sk-kr260-revA",
20 "xlnx,zynqmp-sk-kr260", "xlnx,zynqmp";
Michal Simek8489b6d2023-01-18 13:04:14 +010021 model = "ZynqMP KR260 revA";
Michal Simekbaba22a2022-05-18 12:49:26 +020022
23 ina260-u14 {
24 compatible = "iio-hwmon";
25 io-channels = <&u14 0>, <&u14 1>, <&u14 2>;
26 };
27
28 si5332_0: si5332_0 { /* u17 - GEM0/1 */
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <125000000>;
32 };
33
34 si5332_1: si5332_1 { /* u17 - DP */
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <27000000>;
38 };
39
40 si5332_2: si5332_2 { /* u17 - USB */
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <26000000>;
44 };
45
46 si5332_3: si5332_3 { /* u17 - SFP+ */
47 compatible = "fixed-clock";
48 #clock-cells = <0>;
49 clock-frequency = <156250000>;
50 };
51
52 si5332_4: si5332_4 { /* u17 - GEM2 */
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 };
57
58 si5332_5: si5332_5 { /* u17 - GEM3 */
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <25000000>;
62 };
63};
64
65&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
66 #address-cells = <1>;
67 #size-cells = <0>;
68 pinctrl-names = "default", "gpio";
69 pinctrl-0 = <&pinctrl_i2c1_default>;
70 pinctrl-1 = <&pinctrl_i2c1_gpio>;
Manikanta Guntupalli28dc3562023-07-10 14:37:28 +020071 scl-gpios = <&gpio 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
72 sda-gpios = <&gpio 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
Michal Simekbaba22a2022-05-18 12:49:26 +020073
74 u14: ina260@40 { /* u14 */
75 compatible = "ti,ina260";
76 #io-channel-cells = <1>;
77 label = "ina260-u14";
78 reg = <0x40>;
79 };
80
81 slg7xl45106: gpio@11 { /* u19 - reset logic */
82 compatible = "dlg,slg7xl45106";
83 reg = <0x11>;
84 label = "resetchip";
85 gpio-controller;
86 #gpio-cells = <2>;
87 gpio-line-names = "USB0_PHY_RESET_B", "USB1_PHY_RESET_B",
88 "SD_RESET_B", "USB0_HUB_RESET_B",
89 "USB1_HUB_RESET_B", "PS_GEM0_RESET_B",
90 "PS_GEM1_RESET_B", "";
91 };
92
93 i2c-mux@74 { /* u18 */
94 compatible = "nxp,pca9546";
95 #address-cells = <1>;
96 #size-cells = <0>;
97 reg = <0x74>;
98 usbhub_i2c0: i2c@0 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 reg = <0>;
102 };
103 usbhub_i2c1: i2c@1 {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 reg = <1>;
107 };
108 /* Bus 2/3 are not connected */
109 };
110
111 /* si5332@6a - u17 - clock-generator */
112};
113
114/* GEM SGMII/DP and USB 3.0 */
115&psgtr {
116 status = "okay";
117 /* gem0/1, dp, usb */
118 clocks = <&si5332_0>, <&si5332_1>, <&si5332_2>;
119 clock-names = "ref0", "ref1", "ref2";
120};
121
122&zynqmp_dpsub {
123 status = "okay";
124 phy-names = "dp-phy0";
125 phys = <&psgtr 1 PHY_TYPE_DP 0 1>;
126 assigned-clock-rates = <27000000>, <25000000>, <300000000>;
127};
128
129&zynqmp_dpdma {
130 status = "okay";
131 assigned-clock-rates = <600000000>;
132};
133
134&usb0 { /* mio52 - mio63 */
135 status = "okay";
136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_usb0_default>;
138 phy-names = "usb3-phy";
139 phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
140 reset-gpios = <&slg7xl45106 0 GPIO_ACTIVE_LOW>;
141 assigned-clock-rates = <250000000>, <20000000>;
142
143 usbhub0: usb-hub { /* u43 */
144 i2c-bus = <&usbhub_i2c0>;
145 compatible = "microchip,usb5744";
146 reset-gpios = <&slg7xl45106 3 GPIO_ACTIVE_LOW>;
147 };
148
149 usb2244: usb-sd { /* u38 */
150 compatible = "microchip,usb2244";
151 reset-gpios = <&slg7xl45106 2 GPIO_ACTIVE_LOW>;
152 };
153};
154
155&dwc3_0 {
156 status = "okay";
157 dr_mode = "host";
158 snps,usb3_lpm_capable;
159 maximum-speed = "super-speed";
160};
161
162&usb1 { /* mio64 - mio75 */
163 status = "okay";
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_usb1_default>;
166 phy-names = "usb3-phy";
167 phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
168 reset-gpios = <&slg7xl45106 1 GPIO_ACTIVE_LOW>;
169 assigned-clock-rates = <250000000>, <20000000>;
170
171 usbhub1: usb-hub { /* u84 */
172 i2c-bus = <&usbhub_i2c1>;
173 compatible = "microchip,usb5744";
174 reset-gpios = <&slg7xl45106 4 GPIO_ACTIVE_LOW>;
175 };
176};
177
178&dwc3_1 {
179 status = "okay";
180 dr_mode = "host";
181 snps,usb3_lpm_capable;
182 maximum-speed = "super-speed";
183};
184
185&gem0 { /* mdio mio50/51 */
186 status = "okay";
187 phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>;
188 phy-handle = <&phy0>;
189 phy-mode = "sgmii";
190 is-internal-pcspma;
Harini Katakamf6689612023-07-10 14:37:30 +0200191 assigned-clock-rates = <250000000>;
Michal Simekbaba22a2022-05-18 12:49:26 +0200192};
193
194&gem1 { /* mdio mio50/51, gem mio38 - mio49 */
195 status = "okay";
196 pinctrl-names = "default";
197 pinctrl-0 = <&pinctrl_gem1_default>;
198 phy-handle = <&phy1>;
199 phy-mode = "rgmii-id";
Harini Katakamf6689612023-07-10 14:37:30 +0200200 assigned-clock-rates = <250000000>;
Michal Simekbaba22a2022-05-18 12:49:26 +0200201
202 mdio: mdio {
203 #address-cells = <1>;
204 #size-cells = <0>;
205 phy0: ethernet-phy@4 { /* u81 */
206 #phy-cells = <1>;
207 compatible = "ethernet-phy-id2000.a231";
208 reg = <4>;
209 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
210 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
211 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
212 ti,dp83867-rxctrl-strap-quirk;
Harini Katakam414fc912023-07-10 14:37:32 +0200213 reset-assert-us = <300>;
Michal Simekbaba22a2022-05-18 12:49:26 +0200214 reset-deassert-us = <280>;
215 reset-gpios = <&slg7xl45106 5 GPIO_ACTIVE_LOW>;
216 };
217 phy1: ethernet-phy@8 { /* u36 */
218 #phy-cells = <1>;
219 compatible = "ethernet-phy-id2000.a231";
220 reg = <8>;
221 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
222 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
223 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
224 ti,dp83867-rxctrl-strap-quirk;
225 reset-assert-us = <100>;
226 reset-deassert-us = <280>;
227 reset-gpios = <&slg7xl45106 6 GPIO_ACTIVE_LOW>;
228 };
229 };
230};
231
232/* gem2/gem3 via PL with phys u79@2 and u80@3 */
233
Michal Simekdd0ebfe2023-02-20 09:09:04 +0100234&pinctrl0 {
Michal Simekbaba22a2022-05-18 12:49:26 +0200235 status = "okay";
236
237 pinctrl_uart1_default: uart1-default {
238 conf {
239 groups = "uart1_9_grp";
240 slew-rate = <SLEW_RATE_SLOW>;
241 power-source = <IO_STANDARD_LVCMOS18>;
242 drive-strength = <12>;
243 };
244
245 conf-rx {
246 pins = "MIO37";
247 bias-high-impedance;
248 };
249
250 conf-tx {
251 pins = "MIO36";
252 bias-disable;
253 };
254
255 mux {
256 groups = "uart1_9_grp";
257 function = "uart1";
258 };
259 };
260
261 pinctrl_i2c1_default: i2c1-default {
262 conf {
263 groups = "i2c1_6_grp";
264 bias-pull-up;
265 slew-rate = <SLEW_RATE_SLOW>;
266 power-source = <IO_STANDARD_LVCMOS18>;
267 };
268
269 mux {
270 groups = "i2c1_6_grp";
271 function = "i2c1";
272 };
273 };
274
275 pinctrl_i2c1_gpio: i2c1-gpio {
276 conf {
277 groups = "gpio0_24_grp", "gpio0_25_grp";
278 slew-rate = <SLEW_RATE_SLOW>;
279 power-source = <IO_STANDARD_LVCMOS18>;
280 };
281
282 mux {
283 groups = "gpio0_24_grp", "gpio0_25_grp";
284 function = "gpio0";
285 };
286 };
287
288 pinctrl_gem1_default: gem1-default {
289 conf {
290 groups = "ethernet1_0_grp";
291 slew-rate = <SLEW_RATE_SLOW>;
292 power-source = <IO_STANDARD_LVCMOS18>;
293 };
294
295 conf-rx {
296 pins = "MIO44", "MIO46", "MIO48";
297 bias-high-impedance;
298 low-power-disable;
299 };
300
301 conf-bootstrap {
302 pins = "MIO45", "MIO47", "MIO49";
303 bias-disable;
304 low-power-disable;
305 };
306
307 conf-tx {
308 pins = "MIO38", "MIO39", "MIO40",
309 "MIO41", "MIO42", "MIO43";
310 bias-disable;
311 low-power-enable;
312 };
313
314 conf-mdio {
315 groups = "mdio1_0_grp";
316 slew-rate = <SLEW_RATE_SLOW>;
317 power-source = <IO_STANDARD_LVCMOS18>;
318 bias-disable;
319 };
320
321 mux-mdio {
322 function = "mdio1";
323 groups = "mdio1_0_grp";
324 };
325
326 mux {
327 function = "ethernet1";
328 groups = "ethernet1_0_grp";
329 };
330 };
331
332 pinctrl_usb0_default: usb0-default {
333 conf {
334 groups = "usb0_0_grp";
Michal Simekbaba22a2022-05-18 12:49:26 +0200335 power-source = <IO_STANDARD_LVCMOS18>;
336 };
337
338 conf-rx {
339 pins = "MIO52", "MIO53", "MIO55";
340 bias-high-impedance;
Ashok Reddy Somab8745e72022-06-15 12:16:13 +0200341 drive-strength = <12>;
342 slew-rate = <SLEW_RATE_FAST>;
Michal Simekbaba22a2022-05-18 12:49:26 +0200343 };
344
345 conf-tx {
346 pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
347 "MIO60", "MIO61", "MIO62", "MIO63";
348 bias-disable;
Ashok Reddy Somab8745e72022-06-15 12:16:13 +0200349 drive-strength = <4>;
350 slew-rate = <SLEW_RATE_SLOW>;
Michal Simekbaba22a2022-05-18 12:49:26 +0200351 };
352
353 mux {
354 groups = "usb0_0_grp";
355 function = "usb0";
356 };
357 };
358
359 pinctrl_usb1_default: usb1-default {
360 conf {
361 groups = "usb1_0_grp";
Michal Simekbaba22a2022-05-18 12:49:26 +0200362 power-source = <IO_STANDARD_LVCMOS18>;
363 };
364
365 conf-rx {
366 pins = "MIO64", "MIO65", "MIO67";
367 bias-high-impedance;
Ashok Reddy Somab8745e72022-06-15 12:16:13 +0200368 drive-strength = <12>;
369 slew-rate = <SLEW_RATE_FAST>;
Michal Simekbaba22a2022-05-18 12:49:26 +0200370 };
371
372 conf-tx {
373 pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
374 "MIO72", "MIO73", "MIO74", "MIO75";
375 bias-disable;
Ashok Reddy Somab8745e72022-06-15 12:16:13 +0200376 drive-strength = <4>;
377 slew-rate = <SLEW_RATE_SLOW>;
Michal Simekbaba22a2022-05-18 12:49:26 +0200378 };
379
380 mux {
381 groups = "usb1_0_grp";
382 function = "usb1";
383 };
384 };
385};
386
387&uart1 {
388 status = "okay";
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_uart1_default>;
391};