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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Michal Simek679b9942015-09-30 17:26:55 +02002/*
3 * (C) Copyright 2015 - 2016 Xilinx, Inc.
4 * Michal Simek <michal.simek@xilinx.com>
Michal Simek679b9942015-09-30 17:26:55 +02005 */
6#include <common.h>
Michal Simek49c4c782016-09-08 15:06:22 +02007#include <dm.h>
Michal Simek679b9942015-09-30 17:26:55 +02008#include <ahci.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06009#include <log.h>
Michal Simek679b9942015-09-30 17:26:55 +020010#include <scsi.h>
Michal Simek679b9942015-09-30 17:26:55 +020011#include <asm/io.h>
Peng Mad2ebc382019-04-17 10:10:50 +000012#include <linux/ioport.h>
Michal Simek679b9942015-09-30 17:26:55 +020013
14/* Vendor Specific Register Offsets */
15#define AHCI_VEND_PCFG 0xA4
16#define AHCI_VEND_PPCFG 0xA8
17#define AHCI_VEND_PP2C 0xAC
18#define AHCI_VEND_PP3C 0xB0
19#define AHCI_VEND_PP4C 0xB4
20#define AHCI_VEND_PP5C 0xB8
Yuantian Tang79ed61e2018-07-13 17:25:30 +080021#define AHCI_VEND_AXICC 0xBc
Michal Simek679b9942015-09-30 17:26:55 +020022#define AHCI_VEND_PAXIC 0xC0
23#define AHCI_VEND_PTC 0xC8
24
25/* Vendor Specific Register bit definitions */
26#define PAXIC_ADBW_BW64 0x1
27#define PAXIC_MAWIDD (1 << 8)
28#define PAXIC_MARIDD (1 << 16)
29#define PAXIC_OTL (0x4 << 20)
30
31#define PCFG_TPSS_VAL (0x32 << 16)
32#define PCFG_TPRS_VAL (0x2 << 12)
33#define PCFG_PAD_VAL 0x2
34
35#define PPCFG_TTA 0x1FFFE
36#define PPCFG_PSSO_EN (1 << 28)
37#define PPCFG_PSS_EN (1 << 29)
38#define PPCFG_ESDF_EN (1 << 31)
39
40#define PP2C_CIBGMN 0x0F
41#define PP2C_CIBGMX (0x25 << 8)
42#define PP2C_CIBGN (0x18 << 16)
43#define PP2C_CINMP (0x29 << 24)
44
45#define PP3C_CWBGMN 0x04
46#define PP3C_CWBGMX (0x0B << 8)
47#define PP3C_CWBGN (0x08 << 16)
48#define PP3C_CWNMP (0x0F << 24)
49
50#define PP4C_BMX 0x0a
51#define PP4C_BNM (0x08 << 8)
52#define PP4C_SFD (0x4a << 16)
53#define PP4C_PTST (0x06 << 24)
54
55#define PP5C_RIT 0x60216
56#define PP5C_RCT (0x7f0 << 20)
57
58#define PTC_RX_WM_VAL 0x40
59#define PTC_RSVD (1 << 27)
60
61#define PORT0_BASE 0x100
62#define PORT1_BASE 0x180
63
64/* Port Control Register Bit Definitions */
65#define PORT_SCTL_SPD_GEN3 (0x3 << 4)
66#define PORT_SCTL_SPD_GEN2 (0x2 << 4)
67#define PORT_SCTL_SPD_GEN1 (0x1 << 4)
68#define PORT_SCTL_IPM (0x3 << 8)
69
70#define PORT_BASE 0x100
71#define PORT_OFFSET 0x80
72#define NR_PORTS 2
73#define DRV_NAME "ahci-ceva"
74#define CEVA_FLAG_BROKEN_GEN2 1
75
Yuantian Tang79ed61e2018-07-13 17:25:30 +080076/* flag bit definition */
77#define FLAG_COHERENT 1
78
79/* register config value */
80#define CEVA_PHY1_CFG 0xa003fffe
81#define CEVA_PHY2_CFG 0x28184d1f
82#define CEVA_PHY3_CFG 0x0e081509
83#define CEVA_TRANS_CFG 0x08000029
84#define CEVA_AXICC_CFG 0x3fffffff
85
Peng Madf983a72018-08-01 14:15:43 +080086/* for ls1021a */
Peng Maaaaffe92018-10-22 10:39:49 +080087#define LS1021_AHCI_VEND_AXICC 0xC0
Peng Madf983a72018-08-01 14:15:43 +080088#define LS1021_CEVA_PHY2_CFG 0x28183414
89#define LS1021_CEVA_PHY3_CFG 0x0e080e06
90#define LS1021_CEVA_PHY4_CFG 0x064a080b
91#define LS1021_CEVA_PHY5_CFG 0x2aa86470
92
Peng Mad2ebc382019-04-17 10:10:50 +000093/* ecc val pair */
94#define ECC_DIS_VAL_CH1 0x00020000
Peng Maaaaffe92018-10-22 10:39:49 +080095#define ECC_DIS_VAL_CH2 0x80000000
Peng Mad2ebc382019-04-17 10:10:50 +000096#define ECC_DIS_VAL_CH3 0x40000000
Yuantian Tang79ed61e2018-07-13 17:25:30 +080097
98enum ceva_soc {
99 CEVA_1V84,
100 CEVA_LS1012A,
Peng Madf983a72018-08-01 14:15:43 +0800101 CEVA_LS1021A,
Peng Mad2ebc382019-04-17 10:10:50 +0000102 CEVA_LS1028A,
Peng Ma822d0602018-08-01 11:35:15 +0800103 CEVA_LS1043A,
Peng Ma5fcae592018-10-11 10:34:19 +0000104 CEVA_LS1046A,
Peng Maaaaffe92018-10-22 10:39:49 +0800105 CEVA_LS1088A,
Peng Ma1039d1a2018-10-22 10:43:20 +0800106 CEVA_LS2080A,
Michal Simekc3898a82018-04-06 13:32:52 +0200107};
108
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800109struct ceva_sata_priv {
110 ulong base;
Peng Mad2ebc382019-04-17 10:10:50 +0000111 ulong ecc_base;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800112 enum ceva_soc soc;
113 ulong flag;
114};
115
116static int ceva_init_sata(struct ceva_sata_priv *priv)
Michal Simek679b9942015-09-30 17:26:55 +0200117{
Peng Mad2ebc382019-04-17 10:10:50 +0000118 ulong ecc_addr = priv->ecc_base;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800119 ulong base = priv->base;
Michal Simek679b9942015-09-30 17:26:55 +0200120 ulong tmp;
Michal Simek679b9942015-09-30 17:26:55 +0200121
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800122 switch (priv->soc) {
123 case CEVA_1V84:
124 tmp = PAXIC_ADBW_BW64 | PAXIC_MAWIDD | PAXIC_MARIDD | PAXIC_OTL;
125 writel(tmp, base + AHCI_VEND_PAXIC);
126 tmp = PCFG_TPSS_VAL | PCFG_TPRS_VAL | PCFG_PAD_VAL;
127 writel(tmp, base + AHCI_VEND_PCFG);
Michal Simek679b9942015-09-30 17:26:55 +0200128 tmp = PPCFG_TTA | PPCFG_PSS_EN | PPCFG_ESDF_EN;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800129 writel(tmp, base + AHCI_VEND_PPCFG);
Michal Simek679b9942015-09-30 17:26:55 +0200130 tmp = PTC_RX_WM_VAL | PTC_RSVD;
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800131 writel(tmp, base + AHCI_VEND_PTC);
132 break;
Michal Simek679b9942015-09-30 17:26:55 +0200133
Peng Madf983a72018-08-01 14:15:43 +0800134 case CEVA_LS1021A:
Peng Mad2ebc382019-04-17 10:10:50 +0000135 if (!ecc_addr)
136 return -EINVAL;
137 writel(ECC_DIS_VAL_CH1, ecc_addr);
Peng Madf983a72018-08-01 14:15:43 +0800138 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
139 writel(LS1021_CEVA_PHY2_CFG, base + AHCI_VEND_PP2C);
140 writel(LS1021_CEVA_PHY3_CFG, base + AHCI_VEND_PP3C);
141 writel(LS1021_CEVA_PHY4_CFG, base + AHCI_VEND_PP4C);
142 writel(LS1021_CEVA_PHY5_CFG, base + AHCI_VEND_PP5C);
143 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
Peng Madf983a72018-08-01 14:15:43 +0800144 break;
145
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800146 case CEVA_LS1012A:
Peng Ma822d0602018-08-01 11:35:15 +0800147 case CEVA_LS1043A:
Peng Ma5fcae592018-10-11 10:34:19 +0000148 case CEVA_LS1046A:
Peng Mad2ebc382019-04-17 10:10:50 +0000149 if (!ecc_addr)
150 return -EINVAL;
151 writel(ECC_DIS_VAL_CH2, ecc_addr);
Peng Ma1039d1a2018-10-22 10:43:20 +0800152 /* fallthrough */
153 case CEVA_LS2080A:
Peng Maaaaffe92018-10-22 10:39:49 +0800154 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
155 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
Peng Maaaaffe92018-10-22 10:39:49 +0800156 break;
157
Peng Mad2ebc382019-04-17 10:10:50 +0000158 case CEVA_LS1028A:
Peng Maaaaffe92018-10-22 10:39:49 +0800159 case CEVA_LS1088A:
Peng Mad2ebc382019-04-17 10:10:50 +0000160 if (!ecc_addr)
161 return -EINVAL;
162 writel(ECC_DIS_VAL_CH3, ecc_addr);
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800163 writel(CEVA_PHY1_CFG, base + AHCI_VEND_PPCFG);
164 writel(CEVA_TRANS_CFG, base + AHCI_VEND_PTC);
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800165 break;
Michal Simek679b9942015-09-30 17:26:55 +0200166 }
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800167
Peng Mad2ebc382019-04-17 10:10:50 +0000168 if (priv->flag & FLAG_COHERENT)
169 writel(CEVA_AXICC_CFG, base + AHCI_VEND_AXICC);
170
Michal Simek679b9942015-09-30 17:26:55 +0200171 return 0;
172}
Michal Simek49c4c782016-09-08 15:06:22 +0200173
Michal Simekc3898a82018-04-06 13:32:52 +0200174static int sata_ceva_bind(struct udevice *dev)
175{
176 struct udevice *scsi_dev;
177
178 return ahci_bind_scsi(dev, &scsi_dev);
179}
180
Michal Simek49c4c782016-09-08 15:06:22 +0200181static int sata_ceva_probe(struct udevice *dev)
182{
Michal Simekc3898a82018-04-06 13:32:52 +0200183 struct ceva_sata_priv *priv = dev_get_priv(dev);
Michal Simek49c4c782016-09-08 15:06:22 +0200184
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800185 ceva_init_sata(priv);
Simon Glass7cf1afc2017-06-14 21:28:37 -0600186
Michal Simekc3898a82018-04-06 13:32:52 +0200187 return ahci_probe_scsi(dev, priv->base);
Michal Simek49c4c782016-09-08 15:06:22 +0200188}
189
190static const struct udevice_id sata_ceva_ids[] = {
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800191 { .compatible = "ceva,ahci-1v84", .data = CEVA_1V84 },
192 { .compatible = "fsl,ls1012a-ahci", .data = CEVA_LS1012A },
Peng Madf983a72018-08-01 14:15:43 +0800193 { .compatible = "fsl,ls1021a-ahci", .data = CEVA_LS1021A },
Peng Mad2ebc382019-04-17 10:10:50 +0000194 { .compatible = "fsl,ls1028a-ahci", .data = CEVA_LS1028A },
Peng Ma822d0602018-08-01 11:35:15 +0800195 { .compatible = "fsl,ls1043a-ahci", .data = CEVA_LS1043A },
Peng Ma5fcae592018-10-11 10:34:19 +0000196 { .compatible = "fsl,ls1046a-ahci", .data = CEVA_LS1046A },
Peng Maaaaffe92018-10-22 10:39:49 +0800197 { .compatible = "fsl,ls1088a-ahci", .data = CEVA_LS1088A },
Peng Ma1039d1a2018-10-22 10:43:20 +0800198 { .compatible = "fsl,ls2080a-ahci", .data = CEVA_LS2080A },
Michal Simek49c4c782016-09-08 15:06:22 +0200199 { }
200};
201
202static int sata_ceva_ofdata_to_platdata(struct udevice *dev)
203{
Michal Simekc3898a82018-04-06 13:32:52 +0200204 struct ceva_sata_priv *priv = dev_get_priv(dev);
Peng Mad2ebc382019-04-17 10:10:50 +0000205 struct resource res_regs;
206 int ret;
Michal Simek49c4c782016-09-08 15:06:22 +0200207
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800208 if (dev_read_bool(dev, "dma-coherent"))
209 priv->flag |= FLAG_COHERENT;
210
211 priv->base = dev_read_addr(dev);
Michal Simekc3898a82018-04-06 13:32:52 +0200212 if (priv->base == FDT_ADDR_T_NONE)
Michal Simek49c4c782016-09-08 15:06:22 +0200213 return -EINVAL;
214
Peng Mad2ebc382019-04-17 10:10:50 +0000215 ret = dev_read_resource_byname(dev, "ecc-addr", &res_regs);
216 if (ret)
217 priv->ecc_base = 0;
218 else
219 priv->ecc_base = res_regs.start;
220
Yuantian Tang79ed61e2018-07-13 17:25:30 +0800221 priv->soc = dev_get_driver_data(dev);
222
Peng Mad2ebc382019-04-17 10:10:50 +0000223 debug("ccsr-sata-base %lx\t ecc-base %lx\n",
224 priv->base,
225 priv->ecc_base);
226
Michal Simek49c4c782016-09-08 15:06:22 +0200227 return 0;
228}
229
230U_BOOT_DRIVER(ceva_host_blk) = {
231 .name = "ceva_sata",
Michal Simekc3898a82018-04-06 13:32:52 +0200232 .id = UCLASS_AHCI,
Michal Simek49c4c782016-09-08 15:06:22 +0200233 .of_match = sata_ceva_ids,
Michal Simekc3898a82018-04-06 13:32:52 +0200234 .bind = sata_ceva_bind,
Simon Glassf6ab5a92017-06-14 21:28:43 -0600235 .ops = &scsi_ops,
Michal Simekc3898a82018-04-06 13:32:52 +0200236 .priv_auto_alloc_size = sizeof(struct ceva_sata_priv),
Michal Simek49c4c782016-09-08 15:06:22 +0200237 .probe = sata_ceva_probe,
238 .ofdata_to_platdata = sata_ceva_ofdata_to_platdata,
Michal Simek49c4c782016-09-08 15:06:22 +0200239};