| Hou Zhiqiang | ec70ced | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * P1020RDB-PD Device Tree Source |
| 4 | * |
| 5 | * Copyright 2013 - 2015 Freescale Semiconductor Inc. |
| 6 | * Copyright 2019 NXP |
| 7 | */ |
| 8 | |
| 9 | /include/ "p1020.dtsi" |
| 10 | |
| 11 | / { |
| 12 | model = "fsl,P1020RDB-PD"; |
| 13 | compatible = "fsl,P1020RDB-PD"; |
| 14 | #address-cells = <2>; |
| 15 | #size-cells = <2>; |
| 16 | interrupt-parent = <&mpic>; |
| 17 | |
| 18 | soc: soc@ffe00000 { |
| 19 | ranges = <0x0 0x0 0xffe00000 0x100000>; |
| 20 | }; |
| Hou Zhiqiang | 594708d | 2019-08-27 11:04:04 +0000 | [diff] [blame] | 21 | |
| 22 | pci1: pcie@ffe09000 { |
| 23 | reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ |
| 24 | ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ |
| 25 | 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ |
| 26 | }; |
| 27 | |
| 28 | pci0: pcie@ffe0a000 { |
| 29 | reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ |
| 30 | ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ |
| 31 | 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ |
| 32 | }; |
| Hou Zhiqiang | ec70ced | 2019-08-20 09:35:28 +0000 | [diff] [blame] | 33 | }; |
| 34 | |
| 35 | /include/ "p1020-post.dtsi" |