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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Masahiro Yamada5894ca02014-10-03 19:21:06 +09002/*
Masahiro Yamada928f3242016-08-25 21:03:41 +09003 * Copyright (C) 2012-2014 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
5 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
Masahiro Yamada5894ca02014-10-03 19:21:06 +09006 */
7
8#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07009#include <cpu_func.h>
Masahiro Yamadaf6e7f072015-05-29 17:30:00 +090010#include <linux/io.h>
Masahiro Yamada928f3242016-08-25 21:03:41 +090011#include <asm/secure.h>
Masahiro Yamada107b3fb2016-01-09 01:51:13 +090012
13#include "sc-regs.h"
Masahiro Yamada5894ca02014-10-03 19:21:06 +090014
Masahiro Yamada928f3242016-08-25 21:03:41 +090015/* If PSCI is enabled, this is used for SYSTEM_RESET function */
16#ifdef CONFIG_ARMV7_PSCI
17#define __SECURE __secure
18#else
19#define __SECURE
20#endif
21
22void __SECURE reset_cpu(unsigned long ignored)
Masahiro Yamada5894ca02014-10-03 19:21:06 +090023{
24 u32 tmp;
25
Masahiro Yamada739ba412019-07-10 20:07:41 +090026 writel(5, sc_base + SC_IRQTIMSET); /* default value */
Masahiro Yamada5894ca02014-10-03 19:21:06 +090027
Masahiro Yamada739ba412019-07-10 20:07:41 +090028 tmp = readl(sc_base + SC_SLFRSTSEL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090029 tmp &= ~0x3; /* mask [1:0] */
30 tmp |= 0x0; /* XRST reboot */
Masahiro Yamada739ba412019-07-10 20:07:41 +090031 writel(tmp, sc_base + SC_SLFRSTSEL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090032
Masahiro Yamada739ba412019-07-10 20:07:41 +090033 tmp = readl(sc_base + SC_SLFRSTCTL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090034 tmp |= 0x1;
Masahiro Yamada739ba412019-07-10 20:07:41 +090035 writel(tmp, sc_base + SC_SLFRSTCTL);
Masahiro Yamada5894ca02014-10-03 19:21:06 +090036}