| Dario Binacchi | d09f063 | 2020-12-30 00:06:32 +0100 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0+ |
| 2 | # |
| 3 | # Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> |
| 4 | # |
| 5 | |
| Dario Binacchi | 756d64e | 2020-12-30 00:06:34 +0100 | [diff] [blame] | 6 | config CLK_TI_AM3_DPLL |
| 7 | bool "TI AM33XX Digital Phase-Locked Loop (DPLL) clock drivers" |
| 8 | depends on CLK && OF_CONTROL |
| 9 | help |
| 10 | This enables the DPLL clock drivers support on AM33XX SoCs. The DPLL |
| 11 | provides all interface clocks and functional clocks to the processor. |
| 12 | |
| Dario Binacchi | 215bd54 | 2020-12-30 00:06:39 +0100 | [diff] [blame] | 13 | config CLK_TI_CTRL |
| 14 | bool "TI OMAP4 clock controller" |
| 15 | depends on CLK && OF_CONTROL |
| 16 | help |
| 17 | This enables the clock controller driver support on TI's SoCs. |
| 18 | |
| Dario Binacchi | ea45b8f | 2020-12-30 00:06:35 +0100 | [diff] [blame] | 19 | config CLK_TI_DIVIDER |
| 20 | bool "TI divider clock driver" |
| 21 | depends on CLK && OF_CONTROL && CLK_CCF |
| 22 | help |
| 23 | This enables the divider clock driver support on TI's SoCs. |
| 24 | |
| Dario Binacchi | 58e1af9 | 2020-12-30 00:06:36 +0100 | [diff] [blame] | 25 | config CLK_TI_GATE |
| 26 | bool "TI gate clock driver" |
| 27 | depends on CLK && OF_CONTROL |
| 28 | help |
| 29 | This enables the gate clock driver support on TI's SoCs. |
| 30 | |
| Dario Binacchi | d09f063 | 2020-12-30 00:06:32 +0100 | [diff] [blame] | 31 | config CLK_TI_MUX |
| 32 | bool "TI mux clock driver" |
| 33 | depends on CLK && OF_CONTROL && CLK_CCF |
| 34 | help |
| 35 | This enables the mux clock driver support on TI's SoCs. |
| Dario Binacchi | 52b61c9 | 2020-12-30 00:16:20 +0100 | [diff] [blame] | 36 | |
| 37 | config CLK_TI_SCI |
| 38 | bool "TI System Control Interface (TI SCI) clock driver" |
| 39 | depends on CLK && TI_SCI_PROTOCOL && OF_CONTROL |
| 40 | help |
| 41 | This enables the clock driver support over TI System Control Interface |
| 42 | available on some new TI's SoCs. If you wish to use clock resources |
| 43 | managed by the TI System Controller, say Y here. Otherwise, say N. |
| Tero Kristo | 0aa2930 | 2021-06-11 11:45:13 +0300 | [diff] [blame] | 44 | |
| 45 | config CLK_K3_PLL |
| 46 | bool "PLL clock support for K3 SoC family of devices" |
| 47 | depends on CLK && LIB_RATIONAL |
| 48 | help |
| 49 | Enables PLL clock support for K3 SoC family of devices. |
| 50 | |
| 51 | config SPL_CLK_K3_PLL |
| 52 | bool "PLL clock support for K3 SoC family of devices" |
| 53 | depends on CLK && LIB_RATIONAL && SPL |
| 54 | help |
| 55 | Enables PLL clock support for K3 SoC family of devices. |
| Tero Kristo | b4a72a9 | 2021-06-11 11:45:14 +0300 | [diff] [blame] | 56 | |
| 57 | config CLK_K3 |
| 58 | bool "Clock support for K3 SoC family of devices" |
| 59 | depends on CLK |
| 60 | help |
| 61 | Enables the clock translation layer from DT to device clocks. |
| 62 | |
| 63 | config SPL_CLK_K3 |
| 64 | bool "Clock support for K3 SoC family of devices" |
| 65 | depends on CLK && SPL |
| 66 | help |
| 67 | Enables the clock translation layer from DT to device clocks. |