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Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +02001/*
2 * atmel_lcd.h - Atmel LCD Controller structures
3 *
4 * (C) Copyright 2001
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef _ATMEL_LCD_H_
11#define _ATMEL_LCD_H_
12
Simon Glass9dc89a02016-05-05 07:28:20 -060013/**
14 * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model
15 *
16 * @timing_index: Index of LCD timing to use in device tree node
17 */
18struct atmel_lcd_platdata {
19 int timing_index;
20};
21
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020022typedef struct vidinfo {
23 ushort vl_col; /* Number of columns (i.e. 640) */
24 ushort vl_row; /* Number of rows (i.e. 480) */
Hannes Petermaier604c7d42015-03-27 08:01:38 +010025 ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */
26 u_long vl_clk; /* pixel clock in ps */
Nikita Kiryanovbaaa7dd2015-02-03 13:32:20 +020027
28 /* LCD configuration register */
29 u_long vl_sync; /* Horizontal / vertical sync */
30 u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
31 u_long vl_tft; /* 0 = passive, 1 = TFT */
32 u_long vl_cont_pol_low; /* contrast polarity is low */
33 u_long vl_clk_pol; /* clock polarity */
34
35 /* Horizontal control register. */
36 u_long vl_hsync_len; /* Length of horizontal sync */
37 u_long vl_left_margin; /* Time from sync to picture */
38 u_long vl_right_margin; /* Time from picture to sync */
39
40 /* Vertical control register. */
41 u_long vl_vsync_len; /* Length of vertical sync */
42 u_long vl_upper_margin; /* Time from sync to picture */
43 u_long vl_lower_margin; /* Time from picture to sync */
44
45 u_long mmio; /* Memory mapped registers */
46} vidinfo_t;
47
48#endif