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Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +01001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020027#include <asm/arch/memory-map.h>
28
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010029#define CONFIG_AVR32 1
30#define CONFIG_AT32AP 1
31#define CONFIG_AT32AP7000 1
32#define CONFIG_ATSTK1006 1
33#define CONFIG_ATSTK1000 1
34
35#define CONFIG_ATSTK1000_EXT_FLASH 1
36
37/*
38 * Timer clock frequency. We're using the CPU-internal COUNT register
39 * for this, so this is equivalent to the CPU core clock frequency
40 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_HZ 1000
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010042
43/*
44 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
45 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
46 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010048 */
49#define CONFIG_PLL 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_POWER_MANAGER 1
51#define CONFIG_SYS_OSC0_HZ 20000000
52#define CONFIG_SYS_PLL0_DIV 1
53#define CONFIG_SYS_PLL0_MUL 7
54#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010055/*
56 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010058 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_CLKDIV_CPU 0
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010060/*
61 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010063 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_CLKDIV_HSB 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010065/*
66 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010068 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_CLKDIV_PBA 2
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010070/*
71 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010073 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010075
76/*
77 * The PLLOPT register controls the PLL like this:
78 * icp = PLLOPT<2>
79 * ivco = PLLOPT<1:0>
80 *
81 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
82 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010084
85#undef CONFIG_USART0
86#define CONFIG_USART1 1
87#undef CONFIG_USART2
88#undef CONFIG_USART3
89
90/* User serviceable stuff */
91#define CONFIG_DOS_PARTITION 1
92
93#define CONFIG_CMDLINE_TAG 1
94#define CONFIG_SETUP_MEMORY_TAGS 1
95#define CONFIG_INITRD_TAG 1
96
97#define CONFIG_STACKSIZE (2048)
98
99#define CONFIG_BAUDRATE 115200
100#define CONFIG_BOOTARGS \
101 "console=ttyS0 root=mtd3 fbmem=2400k"
102
103#define CONFIG_BOOTCOMMAND \
104 "fsload; bootm $(fileaddr)"
105
106/*
107 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
108 * data on the serial line may interrupt the boot sequence.
109 */
110#define CONFIG_BOOTDELAY 1
111#define CONFIG_AUTOBOOT 1
112#define CONFIG_AUTOBOOT_KEYED 1
Wolfgang Denkc37207d2008-07-16 16:38:59 +0200113#define CONFIG_AUTOBOOT_PROMPT \
114 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100115#define CONFIG_AUTOBOOT_DELAY_STR "d"
116#define CONFIG_AUTOBOOT_STOP_STR " "
117
118/*
119 * After booting the board for the first time, new ethernet addresses
120 * should be generated and assigned to the environment variables
121 * "ethaddr" and "eth1addr". This is normally done during production.
122 */
123#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
124#define CONFIG_NET_MULTI 1
125
126/*
127 * BOOTP options
128 */
129#define CONFIG_BOOTP_SUBNETMASK
130#define CONFIG_BOOTP_GATEWAY
131
132
133/*
134 * Command line configuration.
135 */
136#include <config_cmd_default.h>
137
138#define CONFIG_CMD_ASKENV
139#define CONFIG_CMD_DHCP
140#define CONFIG_CMD_EXT2
141#define CONFIG_CMD_FAT
142#define CONFIG_CMD_JFFS2
143#define CONFIG_CMD_MMC
144
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100145#undef CONFIG_CMD_FPGA
146#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200147#undef CONFIG_CMD_SOURCE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100148#undef CONFIG_CMD_XIMG
149
150#define CONFIG_ATMEL_USART 1
151#define CONFIG_MACB 1
Haavard Skinnemoenab0df362008-08-29 21:09:49 +0200152#define CONFIG_PORTMUX_PIO 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_NR_PIOS 5
154#define CONFIG_SYS_HSDRAMC 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100155#define CONFIG_MMC 1
Haavard Skinnemoend2d54ea2008-06-12 19:27:57 +0200156#define CONFIG_ATMEL_MCI 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_DCACHE_LINESZ 32
159#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100160
161#define CONFIG_NR_DRAM_BANKS 1
162
163/* External flash on STK1000 */
164#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200166#define CONFIG_FLASH_CFI_DRIVER 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100167#endif
168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_BASE 0x00000000
170#define CONFIG_SYS_FLASH_SIZE 0x800000
171#define CONFIG_SYS_MAX_FLASH_BANKS 1
172#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
177#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
178#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100179
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200180#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200181#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200182#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100183
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_MALLOC_LEN (256*1024)
187#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100188
189/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
191#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100192
193/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_PROMPT "U-Boot> "
195#define CONFIG_SYS_CBSIZE 256
196#define CONFIG_SYS_MAXARGS 16
197#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
198#define CONFIG_SYS_LONGHELP 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100199
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
201#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000)
202#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100203
204#endif /* __CONFIG_H */