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wdenk3b759bd2002-03-31 16:14:24 +00001/*
2 * PowerPC memory management structures
3 */
4
5#ifndef _PPC_MMU_H_
6#define _PPC_MMU_H_
7
8#include <linux/config.h>
9
10#ifndef __ASSEMBLY__
11/* Hardware Page Table Entry */
12typedef struct _PTE {
13#ifdef CONFIG_PPC64BRIDGE
14 unsigned long long vsid:52;
15 unsigned long api:5;
16 unsigned long :5;
17 unsigned long h:1;
18 unsigned long v:1;
19 unsigned long long rpn:52;
20#else /* CONFIG_PPC64BRIDGE */
21 unsigned long v:1; /* Entry is valid */
22 unsigned long vsid:24; /* Virtual segment identifier */
23 unsigned long h:1; /* Hash algorithm indicator */
24 unsigned long api:6; /* Abbreviated page index */
25 unsigned long rpn:20; /* Real (physical) page number */
26#endif /* CONFIG_PPC64BRIDGE */
27 unsigned long :3; /* Unused */
28 unsigned long r:1; /* Referenced */
29 unsigned long c:1; /* Changed */
30 unsigned long w:1; /* Write-thru cache mode */
31 unsigned long i:1; /* Cache inhibited */
32 unsigned long m:1; /* Memory coherence */
33 unsigned long g:1; /* Guarded */
34 unsigned long :1; /* Unused */
35 unsigned long pp:2; /* Page protection */
36} PTE;
37
38/* Values for PP (assumes Ks=0, Kp=1) */
39#define PP_RWXX 0 /* Supervisor read/write, User none */
40#define PP_RWRX 1 /* Supervisor read/write, User read */
41#define PP_RWRW 2 /* Supervisor read/write, User read/write */
42#define PP_RXRX 3 /* Supervisor read, User read */
43
44/* Segment Register */
45typedef struct _SEGREG {
46 unsigned long t:1; /* Normal or I/O type */
47 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
48 unsigned long kp:1; /* User 'key' (normally 1) */
49 unsigned long n:1; /* No-execute */
50 unsigned long :4; /* Unused */
51 unsigned long vsid:24; /* Virtual Segment Identifier */
52} SEGREG;
53
54/* Block Address Translation (BAT) Registers */
55typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
56 unsigned long bepi:15; /* Effective page index (virtual address) */
57 unsigned long :8; /* unused */
58 unsigned long w:1;
59 unsigned long i:1; /* Cache inhibit */
60 unsigned long m:1; /* Memory coherence */
61 unsigned long ks:1; /* Supervisor key (normally 0) */
62 unsigned long kp:1; /* User key (normally 1) */
63 unsigned long pp:2; /* Page access protections */
64} P601_BATU;
65
66typedef struct _BATU { /* Upper part of BAT (all except 601) */
67#ifdef CONFIG_PPC64BRIDGE
68 unsigned long long bepi:47;
69#else /* CONFIG_PPC64BRIDGE */
70 unsigned long bepi:15; /* Effective page index (virtual address) */
71#endif /* CONFIG_PPC64BRIDGE */
72 unsigned long :4; /* Unused */
73 unsigned long bl:11; /* Block size mask */
74 unsigned long vs:1; /* Supervisor valid */
75 unsigned long vp:1; /* User valid */
76} BATU;
77
78typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
79 unsigned long brpn:15; /* Real page index (physical address) */
80 unsigned long :10; /* Unused */
81 unsigned long v:1; /* Valid bit */
82 unsigned long bl:6; /* Block size mask */
83} P601_BATL;
84
85typedef struct _BATL { /* Lower part of BAT (all except 601) */
86#ifdef CONFIG_PPC64BRIDGE
87 unsigned long long brpn:47;
88#else /* CONFIG_PPC64BRIDGE */
89 unsigned long brpn:15; /* Real page index (physical address) */
90#endif /* CONFIG_PPC64BRIDGE */
91 unsigned long :10; /* Unused */
92 unsigned long w:1; /* Write-thru cache */
93 unsigned long i:1; /* Cache inhibit */
94 unsigned long m:1; /* Memory coherence */
95 unsigned long g:1; /* Guarded (MBZ in IBAT) */
96 unsigned long :1; /* Unused */
97 unsigned long pp:2; /* Page access protections */
98} BATL;
99
100typedef struct _BAT {
101 BATU batu; /* Upper register */
102 BATL batl; /* Lower register */
103} BAT;
104
105typedef struct _P601_BAT {
106 P601_BATU batu; /* Upper register */
107 P601_BATL batl; /* Lower register */
108} P601_BAT;
109
110/*
111 * Simulated two-level MMU. This structure is used by the kernel
112 * to keep track of MMU mappings and is used to update/maintain
113 * the hardware HASH table which is really a cache of mappings.
114 *
115 * The simulated structures mimic the hardware available on other
116 * platforms, notably the 80x86 and 680x0.
117 */
118
119typedef struct _pte {
Jon Loeliger5f3249a2006-10-13 16:47:53 -0500120 unsigned long page_num:20;
121 unsigned long flags:12; /* Page flags (some unused bits) */
wdenk3b759bd2002-03-31 16:14:24 +0000122} pte;
123
124#define PD_SHIFT (10+12) /* Page directory */
125#define PD_MASK 0x02FF
126#define PT_SHIFT (12) /* Page Table */
127#define PT_MASK 0x02FF
128#define PG_SHIFT (12) /* Page Entry */
129
130
131/* MMU context */
132
133typedef struct _MMU_context {
134 SEGREG segs[16]; /* Segment registers */
135 pte **pmap; /* Two-level page-map structure */
136} MMU_context;
137
138extern void _tlbie(unsigned long va); /* invalidate a TLB entry */
139extern void _tlbia(void); /* invalidate all TLB entries */
140
141typedef enum {
142 IBAT0 = 0, IBAT1, IBAT2, IBAT3,
Becky Brucec148f242008-05-15 21:29:04 -0500143 DBAT0, DBAT1, DBAT2, DBAT3,
144#ifdef CONFIG_HIGH_BATS
145 IBAT4, IBAT5, IBAT6, IBAT7,
146 DBAT4, DBAT5, DBAT6, DBAT7
147#endif
wdenk3b759bd2002-03-31 16:14:24 +0000148} ppc_bat_t;
149
150extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower);
151extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower);
Becky Bruced5b9b8c2008-05-09 15:41:35 -0500152extern void print_bats(void);
wdenk3b759bd2002-03-31 16:14:24 +0000153
154#endif /* __ASSEMBLY__ */
155
156/* Block size masks */
157#define BL_128K 0x000
158#define BL_256K 0x001
159#define BL_512K 0x003
160#define BL_1M 0x007
161#define BL_2M 0x00F
162#define BL_4M 0x01F
163#define BL_8M 0x03F
164#define BL_16M 0x07F
165#define BL_32M 0x0FF
166#define BL_64M 0x1FF
167#define BL_128M 0x3FF
168#define BL_256M 0x7FF
169
170/* BAT Access Protection */
171#define BPP_XX 0x00 /* No access */
172#define BPP_RX 0x01 /* Read only */
173#define BPP_RW 0x02 /* Read/write */
174
175/* Used to set up SDR1 register */
176#define HASH_TABLE_SIZE_64K 0x00010000
177#define HASH_TABLE_SIZE_128K 0x00020000
178#define HASH_TABLE_SIZE_256K 0x00040000
179#define HASH_TABLE_SIZE_512K 0x00080000
180#define HASH_TABLE_SIZE_1M 0x00100000
181#define HASH_TABLE_SIZE_2M 0x00200000
182#define HASH_TABLE_SIZE_4M 0x00400000
183#define HASH_TABLE_MASK_64K 0x000
184#define HASH_TABLE_MASK_128K 0x001
185#define HASH_TABLE_MASK_256K 0x003
186#define HASH_TABLE_MASK_512K 0x007
187#define HASH_TABLE_MASK_1M 0x00F
188#define HASH_TABLE_MASK_2M 0x01F
189#define HASH_TABLE_MASK_4M 0x03F
190
191/* Control/status registers for the MPC8xx.
192 * A write operation to these registers causes serialized access.
193 * During software tablewalk, the registers used perform mask/shift-add
194 * operations when written/read. A TLB entry is created when the Mx_RPN
195 * is written, and the contents of several registers are used to
196 * create the entry.
197 */
198#define MI_CTR 784 /* Instruction TLB control register */
199#define MI_GPM 0x80000000 /* Set domain manager mode */
200#define MI_PPM 0x40000000 /* Set subpage protection */
201#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
202#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
203#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
204#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
205#define MI_RESETVAL 0x00000000 /* Value of register at reset */
206
207/* These are the Ks and Kp from the PowerPC books. For proper operation,
208 * Ks = 0, Kp = 1.
209 */
210#define MI_AP 786
211#define MI_Ks 0x80000000 /* Should not be set */
212#define MI_Kp 0x40000000 /* Should always be set */
213
214/* The effective page number register. When read, contains the information
215 * about the last instruction TLB miss. When MI_RPN is written, bits in
216 * this register are used to create the TLB entry.
217 */
218#define MI_EPN 787
219#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
220#define MI_EVALID 0x00000200 /* Entry is valid */
221#define MI_ASIDMASK 0x0000000f /* ASID match value */
222 /* Reset value is undefined */
223
224/* A "level 1" or "segment" or whatever you want to call it register.
225 * For the instruction TLB, it contains bits that get loaded into the
226 * TLB entry when the MI_RPN is written.
227 */
228#define MI_TWC 789
229#define MI_APG 0x000001e0 /* Access protection group (0) */
230#define MI_GUARDED 0x00000010 /* Guarded storage */
231#define MI_PSMASK 0x0000000c /* Mask of page size bits */
232#define MI_PS8MEG 0x0000000c /* 8M page size */
233#define MI_PS512K 0x00000004 /* 512K page size */
234#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
235#define MI_SVALID 0x00000001 /* Segment entry is valid */
236 /* Reset value is undefined */
237
238/* Real page number. Defined by the pte. Writing this register
239 * causes a TLB entry to be created for the instruction TLB, using
240 * additional information from the MI_EPN, and MI_TWC registers.
241 */
242#define MI_RPN 790
243
244/* Define an RPN value for mapping kernel memory to large virtual
245 * pages for boot initialization. This has real page number of 0,
246 * large page size, shared page, cache enabled, and valid.
247 * Also mark all subpages valid and write access.
248 */
249#define MI_BOOTINIT 0x000001fd
250
251#define MD_CTR 792 /* Data TLB control register */
252#define MD_GPM 0x80000000 /* Set domain manager mode */
253#define MD_PPM 0x40000000 /* Set subpage protection */
254#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
255#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
256#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
257#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
258#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
259#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
260#define MD_RESETVAL 0x04000000 /* Value of register at reset */
261
262#define M_CASID 793 /* Address space ID (context) to match */
263#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
264
265
266/* These are the Ks and Kp from the PowerPC books. For proper operation,
267 * Ks = 0, Kp = 1.
268 */
269#define MD_AP 794
270#define MD_Ks 0x80000000 /* Should not be set */
271#define MD_Kp 0x40000000 /* Should always be set */
272
273/* The effective page number register. When read, contains the information
274 * about the last instruction TLB miss. When MD_RPN is written, bits in
275 * this register are used to create the TLB entry.
276 */
277#define MD_EPN 795
278#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
279#define MD_EVALID 0x00000200 /* Entry is valid */
280#define MD_ASIDMASK 0x0000000f /* ASID match value */
281 /* Reset value is undefined */
282
283/* The pointer to the base address of the first level page table.
284 * During a software tablewalk, reading this register provides the address
285 * of the entry associated with MD_EPN.
286 */
287#define M_TWB 796
288#define M_L1TB 0xfffff000 /* Level 1 table base address */
289#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
290 /* Reset value is undefined */
291
292/* A "level 1" or "segment" or whatever you want to call it register.
293 * For the data TLB, it contains bits that get loaded into the TLB entry
294 * when the MD_RPN is written. It is also provides the hardware assist
295 * for finding the PTE address during software tablewalk.
296 */
297#define MD_TWC 797
298#define MD_L2TB 0xfffff000 /* Level 2 table base address */
299#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
300#define MD_APG 0x000001e0 /* Access protection group (0) */
301#define MD_GUARDED 0x00000010 /* Guarded storage */
302#define MD_PSMASK 0x0000000c /* Mask of page size bits */
303#define MD_PS8MEG 0x0000000c /* 8M page size */
304#define MD_PS512K 0x00000004 /* 512K page size */
305#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
306#define MD_WT 0x00000002 /* Use writethrough page attribute */
307#define MD_SVALID 0x00000001 /* Segment entry is valid */
308 /* Reset value is undefined */
309
310
311/* Real page number. Defined by the pte. Writing this register
312 * causes a TLB entry to be created for the data TLB, using
313 * additional information from the MD_EPN, and MD_TWC registers.
314 */
315#define MD_RPN 798
316
317/* This is a temporary storage register that could be used to save
318 * a processor working register during a tablewalk.
319 */
320#define M_TW 799
321
322/*
323 * At present, all PowerPC 400-class processors share a similar TLB
324 * architecture. The instruction and data sides share a unified,
325 * 64-entry, fully-associative TLB which is maintained totally under
326 * software control. In addition, the instruction side has a
327 * hardware-managed, 4-entry, fully- associative TLB which serves as a
328 * first level to the shared TLB. These two TLBs are known as the UTLB
329 * and ITLB, respectively.
330 */
331
332#define PPC4XX_TLB_SIZE 64
333
334/*
335 * TLB entries are defined by a "high" tag portion and a "low" data
336 * portion. On all architectures, the data portion is 32-bits.
337 *
338 * TLB entries are managed entirely under software control by reading,
339 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
340 * instructions.
341 */
342
wdenk42d1f032003-10-15 23:53:47 +0000343/*
Kumar Gala1d472732007-12-18 23:21:51 -0600344 * FSL Book-E support
wdenk42d1f032003-10-15 23:53:47 +0000345 */
346
Kumar Gala1d472732007-12-18 23:21:51 -0600347#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
348#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
349#define MAS0_NV(x) ((x) & 0x00000FFF)
wdenk42d1f032003-10-15 23:53:47 +0000350
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200351#define MAS1_VALID 0x80000000
Kumar Gala1d472732007-12-18 23:21:51 -0600352#define MAS1_IPROT 0x40000000
353#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
354#define MAS1_TS 0x00001000
355#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
wdenk42d1f032003-10-15 23:53:47 +0000356
Kumar Gala1d472732007-12-18 23:21:51 -0600357#define MAS2_EPN 0xFFFFF000
358#define MAS2_X0 0x00000040
359#define MAS2_X1 0x00000020
360#define MAS2_W 0x00000010
361#define MAS2_I 0x00000008
362#define MAS2_M 0x00000004
363#define MAS2_G 0x00000002
364#define MAS2_E 0x00000001
wdenk42d1f032003-10-15 23:53:47 +0000365
Kumar Gala1d472732007-12-18 23:21:51 -0600366#define MAS3_RPN 0xFFFFF000
367#define MAS3_U0 0x00000200
368#define MAS3_U1 0x00000100
369#define MAS3_U2 0x00000080
370#define MAS3_U3 0x00000040
371#define MAS3_UX 0x00000020
372#define MAS3_SX 0x00000010
373#define MAS3_UW 0x00000008
374#define MAS3_SW 0x00000004
375#define MAS3_UR 0x00000002
376#define MAS3_SR 0x00000001
wdenk42d1f032003-10-15 23:53:47 +0000377
Kumar Gala1d472732007-12-18 23:21:51 -0600378#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
379#define MAS4_TIDDSEL 0x000F0000
380#define MAS4_TSIZED(x) MAS1_TSIZE(x)
381#define MAS4_X0D 0x00000040
382#define MAS4_X1D 0x00000020
383#define MAS4_WD 0x00000010
384#define MAS4_ID 0x00000008
385#define MAS4_MD 0x00000004
386#define MAS4_GD 0x00000002
387#define MAS4_ED 0x00000001
wdenk42d1f032003-10-15 23:53:47 +0000388
Kumar Gala1d472732007-12-18 23:21:51 -0600389#define MAS6_SPID0 0x3FFF0000
390#define MAS6_SPID1 0x00007FFE
391#define MAS6_SAS 0x00000001
392#define MAS6_SPID MAS6_SPID0
393
394#define MAS7_RPN 0xFFFFFFFF
wdenk42d1f032003-10-15 23:53:47 +0000395
Kumar Gala2146cf52007-12-19 01:18:15 -0600396#define FSL_BOOKE_MAS0(tlbsel,esel,nv) \
397 (MAS0_TLBSEL(tlbsel) | MAS0_ESEL(esel) | MAS0_NV(nv))
398#define FSL_BOOKE_MAS1(v,iprot,tid,ts,tsize) \
399 ((((v) << 31) & MAS1_VALID) |\
400 (((iprot) << 30) & MAS1_IPROT) |\
401 (MAS1_TID(tid)) |\
402 (((ts) << 12) & MAS1_TS) |\
403 (MAS1_TSIZE(tsize)))
404#define FSL_BOOKE_MAS2(epn, wimge) \
405 (((epn) & MAS3_RPN) | (wimge))
406#define FSL_BOOKE_MAS3(rpn, user, perms) \
407 (((rpn) & MAS3_RPN) | (user) | (perms))
408
wdenk42d1f032003-10-15 23:53:47 +0000409#define BOOKE_PAGESZ_1K 0
410#define BOOKE_PAGESZ_4K 1
411#define BOOKE_PAGESZ_16K 2
412#define BOOKE_PAGESZ_64K 3
413#define BOOKE_PAGESZ_256K 4
414#define BOOKE_PAGESZ_1M 5
415#define BOOKE_PAGESZ_4M 6
416#define BOOKE_PAGESZ_16M 7
417#define BOOKE_PAGESZ_64M 8
418#define BOOKE_PAGESZ_256M 9
Andy Fleming45cef612007-02-23 17:11:16 -0600419#define BOOKE_PAGESZ_1G 10
420#define BOOKE_PAGESZ_4G 11
Kumar Gala1d472732007-12-18 23:21:51 -0600421#define BOOKE_PAGESZ_16GB 12
422#define BOOKE_PAGESZ_64GB 13
423#define BOOKE_PAGESZ_256GB 14
424#define BOOKE_PAGESZ_1TB 15
wdenk42d1f032003-10-15 23:53:47 +0000425
Kumar Gala44a23cf2008-01-16 22:33:22 -0600426#ifdef CONFIG_E500
427#ifndef __ASSEMBLY__
428extern void set_tlb(u8 tlb, u32 epn, u64 rpn,
429 u8 perms, u8 wimge,
430 u8 ts, u8 esel, u8 tsize, u8 iprot);
431extern void disable_tlb(u8 esel);
432extern void invalidate_tlb(u8 tlb);
433extern void init_tlbs(void);
Kumar Gala6fb1b732008-06-09 11:07:46 -0500434extern unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg);
Kumar Gala44a23cf2008-01-16 22:33:22 -0600435
Kumar Gala44a23cf2008-01-16 22:33:22 -0600436#define SET_TLB_ENTRY(_tlb, _epn, _rpn, _perms, _wimge, _ts, _esel, _sz, _iprot) \
437 { .tlb = _tlb, .epn = _epn, .rpn = _rpn, .perms = _perms, \
438 .wimge = _wimge, .ts = _ts, .esel = _esel, .tsize = _sz, .iprot = _iprot }
439
440struct fsl_e_tlb_entry {
441 u8 tlb;
442 u32 epn;
443 u64 rpn;
444 u8 perms;
445 u8 wimge;
446 u8 ts;
447 u8 esel;
448 u8 tsize;
449 u8 iprot;
450};
451
452extern struct fsl_e_tlb_entry tlb_table[];
453extern int num_tlb_entries;
454#endif
455#endif
456
Jon Loeligerdebb7352006-04-26 17:58:56 -0500457#if defined(CONFIG_MPC86xx)
Jon Loeliger2c33e8a2006-08-22 17:54:05 -0500458#define LAWBAR_BASE_ADDR 0x00FFFFFF
459#define LAWAR_TRGT_IF 0x01F00000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500460#else
wdenk42d1f032003-10-15 23:53:47 +0000461#define LAWBAR_BASE_ADDR 0x000FFFFF
wdenk42d1f032003-10-15 23:53:47 +0000462#define LAWAR_TRGT_IF 0x00F00000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500463#endif
464#define LAWAR_EN 0x80000000
wdenk42d1f032003-10-15 23:53:47 +0000465#define LAWAR_SIZE 0x0000003F
466
467#define LAWAR_TRGT_IF_PCI 0x00000000
wdenk0ac6f8b2004-07-09 23:27:13 +0000468#define LAWAR_TRGT_IF_PCI1 0x00000000
wdenk42d1f032003-10-15 23:53:47 +0000469#define LAWAR_TRGT_IF_PCIX 0x00000000
wdenk0ac6f8b2004-07-09 23:27:13 +0000470#define LAWAR_TRGT_IF_PCI2 0x00100000
Kumar Galaa853d562007-11-29 02:18:59 -0600471#define LAWAR_TRGT_IF_PCIE1 0x00200000
472#define LAWAR_TRGT_IF_PCIE2 0x00100000
473#define LAWAR_TRGT_IF_PCIE3 0x00300000
wdenk42d1f032003-10-15 23:53:47 +0000474#define LAWAR_TRGT_IF_LBC 0x00400000
475#define LAWAR_TRGT_IF_CCSR 0x00800000
Jon Loeligerdebb7352006-04-26 17:58:56 -0500476#define LAWAR_TRGT_IF_DDR_INTERLEAVED 0x00B00000
wdenk42d1f032003-10-15 23:53:47 +0000477#define LAWAR_TRGT_IF_RIO 0x00c00000
478#define LAWAR_TRGT_IF_DDR 0x00f00000
Jon Loeliger2c33e8a2006-08-22 17:54:05 -0500479#define LAWAR_TRGT_IF_DDR1 0x00f00000
480#define LAWAR_TRGT_IF_DDR2 0x01600000
wdenk42d1f032003-10-15 23:53:47 +0000481
482#define LAWAR_SIZE_BASE 0xa
483#define LAWAR_SIZE_4K (LAWAR_SIZE_BASE+1)
484#define LAWAR_SIZE_8K (LAWAR_SIZE_BASE+2)
485#define LAWAR_SIZE_16K (LAWAR_SIZE_BASE+3)
486#define LAWAR_SIZE_32K (LAWAR_SIZE_BASE+4)
487#define LAWAR_SIZE_64K (LAWAR_SIZE_BASE+5)
488#define LAWAR_SIZE_128K (LAWAR_SIZE_BASE+6)
489#define LAWAR_SIZE_256K (LAWAR_SIZE_BASE+7)
490#define LAWAR_SIZE_512K (LAWAR_SIZE_BASE+8)
491#define LAWAR_SIZE_1M (LAWAR_SIZE_BASE+9)
492#define LAWAR_SIZE_2M (LAWAR_SIZE_BASE+10)
493#define LAWAR_SIZE_4M (LAWAR_SIZE_BASE+11)
494#define LAWAR_SIZE_8M (LAWAR_SIZE_BASE+12)
495#define LAWAR_SIZE_16M (LAWAR_SIZE_BASE+13)
496#define LAWAR_SIZE_32M (LAWAR_SIZE_BASE+14)
497#define LAWAR_SIZE_64M (LAWAR_SIZE_BASE+15)
498#define LAWAR_SIZE_128M (LAWAR_SIZE_BASE+16)
499#define LAWAR_SIZE_256M (LAWAR_SIZE_BASE+17)
500#define LAWAR_SIZE_512M (LAWAR_SIZE_BASE+18)
501#define LAWAR_SIZE_1G (LAWAR_SIZE_BASE+19)
502#define LAWAR_SIZE_2G (LAWAR_SIZE_BASE+20)
Jon Loeliger2c33e8a2006-08-22 17:54:05 -0500503#define LAWAR_SIZE_4G (LAWAR_SIZE_BASE+21)
504#define LAWAR_SIZE_8G (LAWAR_SIZE_BASE+22)
505#define LAWAR_SIZE_16G (LAWAR_SIZE_BASE+23)
506#define LAWAR_SIZE_32G (LAWAR_SIZE_BASE+24)
wdenk42d1f032003-10-15 23:53:47 +0000507
Stefan Roese4037ed32007-02-20 10:43:34 +0100508#ifdef CONFIG_440
509/* General */
510#define TLB_VALID 0x00000200
511
512/* Supported page sizes */
513
514#define SZ_1K 0x00000000
515#define SZ_4K 0x00000010
516#define SZ_16K 0x00000020
517#define SZ_64K 0x00000030
518#define SZ_256K 0x00000040
519#define SZ_1M 0x00000050
520#define SZ_16M 0x00000070
521#define SZ_256M 0x00000090
522
523/* Storage attributes */
524#define SA_W 0x00000800 /* Write-through */
525#define SA_I 0x00000400 /* Caching inhibited */
526#define SA_M 0x00000200 /* Memory coherence */
527#define SA_G 0x00000100 /* Guarded */
528#define SA_E 0x00000080 /* Endian */
529
530/* Access control */
531#define AC_X 0x00000024 /* Execute */
532#define AC_W 0x00000012 /* Write */
533#define AC_R 0x00000009 /* Read */
534
535/* Some handy macros */
536
537#define EPN(e) ((e) & 0xfffffc00)
538#define TLB0(epn,sz) ((EPN((epn)) | (sz) | TLB_VALID ))
539#define TLB1(rpn,erpn) (((rpn) & 0xfffffc00) | (erpn))
540#define TLB2(a) ((a) & 0x00000fbf)
541
542#define tlbtab_start\
543 mflr r1 ;\
544 bl 0f ;
545
546#define tlbtab_end\
547 .long 0, 0, 0 ;\
5480: mflr r0 ;\
549 mtlr r1 ;\
550 blr ;
551
552#define tlbentry(epn,sz,rpn,erpn,attr)\
553 .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
554
555/*----------------------------------------------------------------------------+
556| TLB specific defines.
557+----------------------------------------------------------------------------*/
Stefan Roese84a999b2008-02-19 22:01:57 +0100558#define TLB_256MB_ALIGN_MASK 0xFF0000000ULL
559#define TLB_16MB_ALIGN_MASK 0xFFF000000ULL
560#define TLB_1MB_ALIGN_MASK 0xFFFF00000ULL
561#define TLB_256KB_ALIGN_MASK 0xFFFFC0000ULL
562#define TLB_64KB_ALIGN_MASK 0xFFFFF0000ULL
563#define TLB_16KB_ALIGN_MASK 0xFFFFFC000ULL
564#define TLB_4KB_ALIGN_MASK 0xFFFFFF000ULL
565#define TLB_1KB_ALIGN_MASK 0xFFFFFFC00ULL
Stefan Roese4037ed32007-02-20 10:43:34 +0100566#define TLB_256MB_SIZE 0x10000000
567#define TLB_16MB_SIZE 0x01000000
568#define TLB_1MB_SIZE 0x00100000
569#define TLB_256KB_SIZE 0x00040000
570#define TLB_64KB_SIZE 0x00010000
571#define TLB_16KB_SIZE 0x00004000
572#define TLB_4KB_SIZE 0x00001000
573#define TLB_1KB_SIZE 0x00000400
574
575#define TLB_WORD0_EPN_MASK 0xFFFFFC00
576#define TLB_WORD0_EPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
577#define TLB_WORD0_EPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
578#define TLB_WORD0_V_MASK 0x00000200
579#define TLB_WORD0_V_ENABLE 0x00000200
580#define TLB_WORD0_V_DISABLE 0x00000000
581#define TLB_WORD0_TS_MASK 0x00000100
582#define TLB_WORD0_TS_1 0x00000100
583#define TLB_WORD0_TS_0 0x00000000
584#define TLB_WORD0_SIZE_MASK 0x000000F0
585#define TLB_WORD0_SIZE_1KB 0x00000000
586#define TLB_WORD0_SIZE_4KB 0x00000010
587#define TLB_WORD0_SIZE_16KB 0x00000020
588#define TLB_WORD0_SIZE_64KB 0x00000030
589#define TLB_WORD0_SIZE_256KB 0x00000040
590#define TLB_WORD0_SIZE_1MB 0x00000050
591#define TLB_WORD0_SIZE_16MB 0x00000070
592#define TLB_WORD0_SIZE_256MB 0x00000090
593#define TLB_WORD0_TPAR_MASK 0x0000000F
594#define TLB_WORD0_TPAR_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
595#define TLB_WORD0_TPAR_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
596
597#define TLB_WORD1_RPN_MASK 0xFFFFFC00
598#define TLB_WORD1_RPN_ENCODE(n) (((unsigned long)(n))&0xFFFFFC00)
599#define TLB_WORD1_RPN_DECODE(n) (((unsigned long)(n))&0xFFFFFC00)
600#define TLB_WORD1_PAR1_MASK 0x00000300
601#define TLB_WORD1_PAR1_ENCODE(n) ((((unsigned long)(n))&0x03)<<8)
602#define TLB_WORD1_PAR1_DECODE(n) ((((unsigned long)(n))>>8)&0x03)
603#define TLB_WORD1_PAR1_0 0x00000000
604#define TLB_WORD1_PAR1_1 0x00000100
605#define TLB_WORD1_PAR1_2 0x00000200
606#define TLB_WORD1_PAR1_3 0x00000300
607#define TLB_WORD1_ERPN_MASK 0x0000000F
608#define TLB_WORD1_ERPN_ENCODE(n) ((((unsigned long)(n))&0x0F)<<0)
609#define TLB_WORD1_ERPN_DECODE(n) ((((unsigned long)(n))>>0)&0x0F)
610
611#define TLB_WORD2_PAR2_MASK 0xC0000000
612#define TLB_WORD2_PAR2_ENCODE(n) ((((unsigned long)(n))&0x03)<<30)
613#define TLB_WORD2_PAR2_DECODE(n) ((((unsigned long)(n))>>30)&0x03)
614#define TLB_WORD2_PAR2_0 0x00000000
615#define TLB_WORD2_PAR2_1 0x40000000
616#define TLB_WORD2_PAR2_2 0x80000000
617#define TLB_WORD2_PAR2_3 0xC0000000
618#define TLB_WORD2_U0_MASK 0x00008000
619#define TLB_WORD2_U0_ENABLE 0x00008000
620#define TLB_WORD2_U0_DISABLE 0x00000000
621#define TLB_WORD2_U1_MASK 0x00004000
622#define TLB_WORD2_U1_ENABLE 0x00004000
623#define TLB_WORD2_U1_DISABLE 0x00000000
624#define TLB_WORD2_U2_MASK 0x00002000
625#define TLB_WORD2_U2_ENABLE 0x00002000
626#define TLB_WORD2_U2_DISABLE 0x00000000
627#define TLB_WORD2_U3_MASK 0x00001000
628#define TLB_WORD2_U3_ENABLE 0x00001000
629#define TLB_WORD2_U3_DISABLE 0x00000000
630#define TLB_WORD2_W_MASK 0x00000800
631#define TLB_WORD2_W_ENABLE 0x00000800
632#define TLB_WORD2_W_DISABLE 0x00000000
633#define TLB_WORD2_I_MASK 0x00000400
634#define TLB_WORD2_I_ENABLE 0x00000400
635#define TLB_WORD2_I_DISABLE 0x00000000
636#define TLB_WORD2_M_MASK 0x00000200
637#define TLB_WORD2_M_ENABLE 0x00000200
638#define TLB_WORD2_M_DISABLE 0x00000000
639#define TLB_WORD2_G_MASK 0x00000100
640#define TLB_WORD2_G_ENABLE 0x00000100
641#define TLB_WORD2_G_DISABLE 0x00000000
642#define TLB_WORD2_E_MASK 0x00000080
643#define TLB_WORD2_E_ENABLE 0x00000080
644#define TLB_WORD2_E_DISABLE 0x00000000
645#define TLB_WORD2_UX_MASK 0x00000020
646#define TLB_WORD2_UX_ENABLE 0x00000020
647#define TLB_WORD2_UX_DISABLE 0x00000000
648#define TLB_WORD2_UW_MASK 0x00000010
649#define TLB_WORD2_UW_ENABLE 0x00000010
650#define TLB_WORD2_UW_DISABLE 0x00000000
651#define TLB_WORD2_UR_MASK 0x00000008
652#define TLB_WORD2_UR_ENABLE 0x00000008
653#define TLB_WORD2_UR_DISABLE 0x00000000
654#define TLB_WORD2_SX_MASK 0x00000004
655#define TLB_WORD2_SX_ENABLE 0x00000004
656#define TLB_WORD2_SX_DISABLE 0x00000000
657#define TLB_WORD2_SW_MASK 0x00000002
658#define TLB_WORD2_SW_ENABLE 0x00000002
659#define TLB_WORD2_SW_DISABLE 0x00000000
660#define TLB_WORD2_SR_MASK 0x00000001
661#define TLB_WORD2_SR_ENABLE 0x00000001
662#define TLB_WORD2_SR_DISABLE 0x00000000
663
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200664/*----------------------------------------------------------------------------+
665| Following instructions are not available in Book E mode of the GNU assembler.
666+----------------------------------------------------------------------------*/
667#define DCCCI(ra,rb) .long 0x7c000000|\
668 (ra<<16)|(rb<<11)|(454<<1)
669
670#define ICCCI(ra,rb) .long 0x7c000000|\
671 (ra<<16)|(rb<<11)|(966<<1)
672
673#define DCREAD(rt,ra,rb) .long 0x7c000000|\
674 (rt<<21)|(ra<<16)|(rb<<11)|(486<<1)
675
676#define ICREAD(ra,rb) .long 0x7c000000|\
677 (ra<<16)|(rb<<11)|(998<<1)
678
679#define TLBSX(rt,ra,rb) .long 0x7c000000|\
680 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
681
682#define TLBWE(rs,ra,ws) .long 0x7c000000|\
683 (rs<<21)|(ra<<16)|(ws<<11)|(978<<1)
684
685#define TLBRE(rt,ra,ws) .long 0x7c000000|\
686 (rt<<21)|(ra<<16)|(ws<<11)|(946<<1)
687
688#define TLBSXDOT(rt,ra,rb) .long 0x7c000001|\
689 (rt<<21)|(ra<<16)|(rb<<11)|(914<<1)
690
691#define MSYNC .long 0x7c000000|\
692 (598<<1)
693
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200694#define MBAR_INST .long 0x7c000000|\
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200695 (854<<1)
696
Stefan Roese4037ed32007-02-20 10:43:34 +0100697#ifndef __ASSEMBLY__
698/* Prototypes */
699void mttlb1(unsigned long index, unsigned long value);
700void mttlb2(unsigned long index, unsigned long value);
701void mttlb3(unsigned long index, unsigned long value);
702unsigned long mftlb1(unsigned long index);
703unsigned long mftlb2(unsigned long index);
704unsigned long mftlb3(unsigned long index);
Stefan Roese5743a922007-07-16 08:53:51 +0200705
Stefan Roese84a999b2008-02-19 22:01:57 +0100706void program_tlb(u64 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
Stefan Roese5743a922007-07-16 08:53:51 +0200707void remove_tlb(u32 vaddr, u32 size);
Stefan Roese483e09a2007-10-31 17:59:22 +0100708void change_tlb(u32 vaddr, u32 size, u32 tlb_word2_i_value);
Stefan Roese4037ed32007-02-20 10:43:34 +0100709#endif /* __ASSEMBLY__ */
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200710
Stefan Roese4037ed32007-02-20 10:43:34 +0100711#endif /* CONFIG_440 */
wdenk3b759bd2002-03-31 16:14:24 +0000712#endif /* _PPC_MMU_H_ */