blob: c20d54a3c5b8520fccac7a65e70e2f8c878a1981 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0 */
Ley Foon Tan1b259402017-04-26 02:44:46 +08002/*
Tien Fong Cheeda0d5f62019-05-07 17:42:32 +08003 * Copyright (C) 2015-2019 Altera Corporation <www.altera.com>
Ley Foon Tan1b259402017-04-26 02:44:46 +08004 */
5
6#ifndef __CONFIG_SOCFGPA_ARRIA10_H__
7#define __CONFIG_SOCFGPA_ARRIA10_H__
8
9#include <asm/arch/base_addr_a10.h>
Tom Rini91d27a12017-06-02 11:03:50 -040010
Ley Foon Tan1b259402017-04-26 02:44:46 +080011/*
12 * U-Boot general configurations
13 */
Ley Foon Tan1b259402017-04-26 02:44:46 +080014
15/* Memory configurations */
16#define PHYS_SDRAM_1_SIZE 0x40000000
17
Ley Foon Tan1b259402017-04-26 02:44:46 +080018/*
Ley Foon Tan1b259402017-04-26 02:44:46 +080019 * Serial / UART configurations
20 */
21#define CONFIG_SYS_NS16550_MEM32
22#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
23
24/*
25 * L4 OSC1 Timer 0
26 */
27/* reload value when timer count to zero */
28#define TIMER_LOAD_VAL 0xFFFFFFFF
29
30/*
31 * Flash configurations
32 */
Ley Foon Tan1b259402017-04-26 02:44:46 +080033
Tien Fong Cheeda0d5f62019-05-07 17:42:32 +080034/* SPL memory allocation configuration, this is for FAT implementation */
35#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
36
Ley Foon Tan1b259402017-04-26 02:44:46 +080037/* The rest of the configuration is shared */
38#include <configs/socfpga_common.h>
39
40#endif /* __CONFIG_SOCFGPA_ARRIA10_H__ */