blob: 014a7c98fcc000b931909887245e5a627688b05a [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +02002/*
3 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Sedji Gaouaou22ee6472009-07-09 10:16:29 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
Sedji Gaouaou22ee6472009-07-09 10:16:29 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* ARM asynchronous clock */
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000014#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
15#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020016
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000017/* general purpose I/O */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020018
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020019/* LCD */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020020#define LCD_BPP LCD_COLOR8
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020021
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020022/* SDRAM */
Wenyou Yange61ed482017-09-14 11:07:42 +080023#define CONFIG_SYS_SDRAM_BASE 0x70000000
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000024#define CONFIG_SYS_SDRAM_SIZE 0x08000000
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020025
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000026#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang59b37122017-04-18 15:15:48 +080027 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020028
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020029/* NAND flash */
30#ifdef CONFIG_CMD_NAND
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020031#define CONFIG_SYS_MAX_NAND_DEVICE 1
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000032#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
33#define CONFIG_SYS_NAND_DBW_8
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020034/* our ALE is AD21 */
35#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
36/* our CLE is AD22 */
37#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
38#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
39#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +020040
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020041#endif
42
Wenyou Yang55415432017-09-14 11:07:44 +080043#ifdef CONFIG_NAND_BOOT
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000044/* bootstrap + u-boot + env in nandflash */
Wenyou Yang55415432017-09-14 11:07:44 +080045#elif CONFIG_SD_BOOT
Wu, Josh9637a1b2014-05-21 10:42:16 +080046/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh9637a1b2014-05-21 10:42:16 +080047#endif
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020048
Bo Shen41d41a92015-03-27 14:23:34 +080049/* Defines for SPL */
Bo Shen41d41a92015-03-27 14:23:34 +080050#define CONFIG_SPL_MAX_SIZE 0x010000
51#define CONFIG_SPL_STACK 0x310000
52
Bo Shen41d41a92015-03-27 14:23:34 +080053#define CONFIG_SYS_MONITOR_LEN 0x80000
54
Wenyou Yang55415432017-09-14 11:07:44 +080055#ifdef CONFIG_SD_BOOT
Bo Shen41d41a92015-03-27 14:23:34 +080056
57#define CONFIG_SPL_BSS_START_ADDR 0x70000000
58#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
59#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
60#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
61
Bo Shen41d41a92015-03-27 14:23:34 +080062#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen41d41a92015-03-27 14:23:34 +080063
Wenyou Yang55415432017-09-14 11:07:44 +080064#elif CONFIG_NAND_BOOT
Bo Shen41d41a92015-03-27 14:23:34 +080065#define CONFIG_SPL_NAND_SOFTECC
Bo Shen41d41a92015-03-27 14:23:34 +080066#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
Bo Shen41d41a92015-03-27 14:23:34 +080067
Bo Shen41d41a92015-03-27 14:23:34 +080068#define CONFIG_SYS_NAND_ECCSIZE 256
69#define CONFIG_SYS_NAND_ECCBYTES 3
Bo Shen41d41a92015-03-27 14:23:34 +080070#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
71 48, 49, 50, 51, 52, 53, 54, 55, \
72 56, 57, 58, 59, 60, 61, 62, 63, }
73#endif
74
Bo Shen41d41a92015-03-27 14:23:34 +080075#define CONFIG_SYS_MASTER_CLOCK 132096000
76#define CONFIG_SYS_AT91_PLLA 0x20c73f03
77#define CONFIG_SYS_MCKR 0x1301
78#define CONFIG_SYS_MCKR_CSS 0x1302
79
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020080#endif