blob: 32d3b584bce1059f1eb8808da37f845937fbf364 [file] [log] [blame]
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +09001/*
2 * board/renesas/koelsch/koelsch.c
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 *
8 */
9
10#include <common.h>
11#include <malloc.h>
12#include <asm/processor.h>
13#include <asm/mach-types.h>
14#include <asm/io.h>
15#include <asm/errno.h>
16#include <asm/arch/sys_proto.h>
17#include <asm/gpio.h>
18#include <asm/arch/rmobile.h>
Nobuhiro Iwamatsu90362c02013-10-20 20:37:17 +090019#include <netdev.h>
20#include <miiphy.h>
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +090021#include <i2c.h>
22#include "qos.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26#define s_init_wait(cnt) \
27 ({ \
28 u32 i = 0x10000 * cnt; \
29 while (i > 0) \
30 i--; \
31 })
32
33
34#define dbpdrgd_check(bsc) \
35 ({ \
36 while ((readl(&bsc->dbpdrgd) & 0x1) != 0x1) \
37 ; \
38 })
39
40#if defined(CONFIG_NORFLASH)
41static void bsc_init(void)
42{
43 struct r8a7791_lbsc *lbsc = (struct r8a7791_lbsc *)LBSC_BASE;
44 struct r8a7791_dbsc3 *dbsc3_0 = (struct r8a7791_dbsc3 *)DBSC3_0_BASE;
45
46 /* LBSC */
47 writel(0x00000020, &lbsc->cs0ctrl);
48 writel(0x00000020, &lbsc->cs1ctrl);
49 writel(0x00002020, &lbsc->ecs0ctrl);
50 writel(0x00002020, &lbsc->ecs1ctrl);
51
52 writel(0x077F077F, &lbsc->cswcr0);
53 writel(0x077F077F, &lbsc->cswcr1);
54 writel(0x077F077F, &lbsc->ecswcr0);
55 writel(0x077F077F, &lbsc->ecswcr1);
56
57 /* DBSC3 */
58 s_init_wait(10);
59
60 writel(0x0000A55A, &dbsc3_0->dbpdlck);
61 writel(0x00000001, &dbsc3_0->dbpdrga);
62 writel(0x80000000, &dbsc3_0->dbpdrgd);
63 writel(0x00000004, &dbsc3_0->dbpdrga);
64 dbpdrgd_check(dbsc3_0);
65
66 writel(0x00000006, &dbsc3_0->dbpdrga);
67 writel(0x0001C000, &dbsc3_0->dbpdrgd);
68
69 writel(0x00000023, &dbsc3_0->dbpdrga);
70 writel(0x00FD2480, &dbsc3_0->dbpdrgd);
71
72 writel(0x00000010, &dbsc3_0->dbpdrga);
73 writel(0xF004649B, &dbsc3_0->dbpdrgd);
74
75 writel(0x0000000F, &dbsc3_0->dbpdrga);
76 writel(0x00181EE4, &dbsc3_0->dbpdrgd);
77
78 writel(0x0000000E, &dbsc3_0->dbpdrga);
79 writel(0x33C03812, &dbsc3_0->dbpdrgd);
80
81 writel(0x00000003, &dbsc3_0->dbpdrga);
82 writel(0x0300C481, &dbsc3_0->dbpdrgd);
83
84 writel(0x00000007, &dbsc3_0->dbkind);
85 writel(0x10030A02, &dbsc3_0->dbconf0);
86 writel(0x00000001, &dbsc3_0->dbphytype);
87 writel(0x00000000, &dbsc3_0->dbbl);
88 writel(0x0000000B, &dbsc3_0->dbtr0);
89 writel(0x00000008, &dbsc3_0->dbtr1);
90 writel(0x00000000, &dbsc3_0->dbtr2);
91 writel(0x0000000B, &dbsc3_0->dbtr3);
92 writel(0x000C000B, &dbsc3_0->dbtr4);
93 writel(0x00000027, &dbsc3_0->dbtr5);
94 writel(0x0000001C, &dbsc3_0->dbtr6);
95 writel(0x00000005, &dbsc3_0->dbtr7);
96 writel(0x00000018, &dbsc3_0->dbtr8);
97 writel(0x00000008, &dbsc3_0->dbtr9);
98 writel(0x0000000C, &dbsc3_0->dbtr10);
99 writel(0x00000009, &dbsc3_0->dbtr11);
100 writel(0x00000012, &dbsc3_0->dbtr12);
101 writel(0x000000D0, &dbsc3_0->dbtr13);
102 writel(0x00140005, &dbsc3_0->dbtr14);
103 writel(0x00050004, &dbsc3_0->dbtr15);
104 writel(0x70233005, &dbsc3_0->dbtr16);
105 writel(0x000C0000, &dbsc3_0->dbtr17);
106 writel(0x00000300, &dbsc3_0->dbtr18);
107 writel(0x00000040, &dbsc3_0->dbtr19);
108 writel(0x00000001, &dbsc3_0->dbrnk0);
109 writel(0x00020001, &dbsc3_0->dbadj0);
110 writel(0x20082008, &dbsc3_0->dbadj2);
111 writel(0x00020002, &dbsc3_0->dbwt0cnf0);
112 writel(0x0000000F, &dbsc3_0->dbwt0cnf4);
113
114 writel(0x00000015, &dbsc3_0->dbpdrga);
115 writel(0x00000D70, &dbsc3_0->dbpdrgd);
116
117 writel(0x00000016, &dbsc3_0->dbpdrga);
118 writel(0x00000006, &dbsc3_0->dbpdrgd);
119
120 writel(0x00000017, &dbsc3_0->dbpdrga);
121 writel(0x00000018, &dbsc3_0->dbpdrgd);
122
123 writel(0x00000012, &dbsc3_0->dbpdrga);
124 writel(0x9D5CBB66, &dbsc3_0->dbpdrgd);
125
126 writel(0x00000013, &dbsc3_0->dbpdrga);
127 writel(0x1A868300, &dbsc3_0->dbpdrgd);
128
129 writel(0x00000023, &dbsc3_0->dbpdrga);
130 writel(0x00FDB6C0, &dbsc3_0->dbpdrgd);
131
132 writel(0x00000014, &dbsc3_0->dbpdrga);
133 writel(0x300214D8, &dbsc3_0->dbpdrgd);
134
135 writel(0x0000001A, &dbsc3_0->dbpdrga);
136 writel(0x930035C7, &dbsc3_0->dbpdrgd);
137
138 writel(0x00000060, &dbsc3_0->dbpdrga);
139 writel(0x330657B2, &dbsc3_0->dbpdrgd);
140
141 writel(0x00000011, &dbsc3_0->dbpdrga);
142 writel(0x1000040B, &dbsc3_0->dbpdrgd);
143
144 writel(0x0000FA00, &dbsc3_0->dbcmd);
145 writel(0x00000001, &dbsc3_0->dbpdrga);
146 writel(0x00000071, &dbsc3_0->dbpdrgd);
147
148 writel(0x00000004, &dbsc3_0->dbpdrga);
149 dbpdrgd_check(dbsc3_0);
150
151 writel(0x0000FA00, &dbsc3_0->dbcmd);
152 writel(0x2100FA00, &dbsc3_0->dbcmd);
153 writel(0x0000FA00, &dbsc3_0->dbcmd);
154 writel(0x0000FA00, &dbsc3_0->dbcmd);
155 writel(0x0000FA00, &dbsc3_0->dbcmd);
156 writel(0x0000FA00, &dbsc3_0->dbcmd);
157 writel(0x0000FA00, &dbsc3_0->dbcmd);
158 writel(0x0000FA00, &dbsc3_0->dbcmd);
159 writel(0x0000FA00, &dbsc3_0->dbcmd);
160
161 writel(0x110000DB, &dbsc3_0->dbcmd);
162
163 writel(0x00000001, &dbsc3_0->dbpdrga);
164 writel(0x00000181, &dbsc3_0->dbpdrgd);
165
166 writel(0x00000004, &dbsc3_0->dbpdrga);
167 dbpdrgd_check(dbsc3_0);
168
169 writel(0x00000001, &dbsc3_0->dbpdrga);
170 writel(0x0000FE01, &dbsc3_0->dbpdrgd);
171
172 writel(0x00000004, &dbsc3_0->dbpdrga);
173 dbpdrgd_check(dbsc3_0);
174
175 writel(0x00000000, &dbsc3_0->dbbs0cnt1);
176 writel(0x01004C20, &dbsc3_0->dbcalcnf);
177 writel(0x014000AA, &dbsc3_0->dbcaltr);
178 writel(0x00000140, &dbsc3_0->dbrfcnf0);
179 writel(0x00081860, &dbsc3_0->dbrfcnf1);
180 writel(0x00010000, &dbsc3_0->dbrfcnf2);
181 writel(0x00000001, &dbsc3_0->dbrfen);
182 writel(0x00000001, &dbsc3_0->dbacen);
183}
184#else
185#define bsc_init() do {} while (0)
186#endif /* CONFIG_NORFLASH */
187
188void s_init(void)
189{
190 struct r8a7791_rwdt *rwdt = (struct r8a7791_rwdt *)RWDT_BASE;
191 struct r8a7791_swdt *swdt = (struct r8a7791_swdt *)SWDT_BASE;
192
193 /* Watchdog init */
194 writel(0xA5A5A500, &rwdt->rwtcsra);
195 writel(0xA5A5A500, &swdt->swtcsra);
196
197 /* QoS */
198 qos_init();
199
200 /* BSC */
201 bsc_init();
202}
203
204#define MSTPSR1 0xE6150038
205#define SMSTPCR1 0xE6150134
206#define TMU0_MSTP125 (1 << 25)
207
208#define MSTPSR7 0xE61501C4
209#define SMSTPCR7 0xE615014C
210#define SCIF0_MSTP721 (1 << 21)
211
Nobuhiro Iwamatsu90362c02013-10-20 20:37:17 +0900212#define MSTPSR8 0xE61509A0
213#define SMSTPCR8 0xE6150990
214#define ETHER_MSTP813 (1 << 13)
215
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +0900216#define PMMR 0xE6060000
217#define GPSR4 0xE6060014
218#define IPSR14 0xE6060058
219
220#define set_guard_reg(addr, mask, value) \
221{ \
222 u32 val; \
223 val = (readl(addr) & ~(mask)) | (value); \
224 writel(~val, PMMR); \
225 writel(val, addr); \
226}
227
228#define mstp_setbits(type, addr, saddr, set) \
229 out_##type((saddr), in_##type(addr) | (set))
230#define mstp_clrbits(type, addr, saddr, clear) \
231 out_##type((saddr), in_##type(addr) & ~(clear))
232#define mstp_setbits_le32(addr, saddr, set) \
233 mstp_setbits(le32, addr, saddr, set)
234#define mstp_clrbits_le32(addr, saddr, clear) \
235 mstp_clrbits(le32, addr, saddr, clear)
236
237int board_early_init_f(void)
238{
239 mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
240
241#if defined(CONFIG_NORFLASH)
242 /* SCIF0 */
243 set_guard_reg(GPSR4, 0x34000000, 0x00000000);
244 set_guard_reg(IPSR14, 0x00000FC7, 0x00000481);
245 set_guard_reg(GPSR4, 0x00000000, 0x34000000);
246#endif
247
248 mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
249
Nobuhiro Iwamatsu90362c02013-10-20 20:37:17 +0900250 /* ETHER */
251 mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
252
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +0900253 return 0;
254}
255
Nobuhiro Iwamatsu9f861f02013-10-11 14:49:04 +0900256void arch_preboot_os(void)
257{
258 /* Disable TMU0 */
259 mstp_setbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
260}
261
Nobuhiro Iwamatsu90362c02013-10-20 20:37:17 +0900262/* LSI pin pull-up control */
263#define PUPR5 0xe6060114
264#define PUPR5_ETH 0x3FFC0000
265#define PUPR5_ETH_MAGIC (1 << 27)
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +0900266int board_init(void)
267{
268 /* adress of boot parameters */
269 gd->bd->bi_boot_params = KOELSCH_SDRAM_BASE + 0x100;
270
271 /* Init PFC controller */
272 r8a7791_pinmux_init();
273
Nobuhiro Iwamatsu90362c02013-10-20 20:37:17 +0900274 /* ETHER Enable */
275 gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
276 gpio_request(GPIO_FN_ETH_RX_ER, NULL);
277 gpio_request(GPIO_FN_ETH_RXD0, NULL);
278 gpio_request(GPIO_FN_ETH_RXD1, NULL);
279 gpio_request(GPIO_FN_ETH_LINK, NULL);
280 gpio_request(GPIO_FN_ETH_REFCLK, NULL);
281 gpio_request(GPIO_FN_ETH_MDIO, NULL);
282 gpio_request(GPIO_FN_ETH_TXD1, NULL);
283 gpio_request(GPIO_FN_ETH_TX_EN, NULL);
284 gpio_request(GPIO_FN_ETH_TXD0, NULL);
285 gpio_request(GPIO_FN_ETH_MDC, NULL);
286 gpio_request(GPIO_FN_IRQ0, NULL);
287
288 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
289 gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
290 mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
291
292 gpio_direction_output(GPIO_GP_5_22, 0);
293 mdelay(20);
294 gpio_set_value(GPIO_GP_5_22, 1);
295 udelay(1);
296
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +0900297 return 0;
298}
299
Nobuhiro Iwamatsu90362c02013-10-20 20:37:17 +0900300#define CXR24 0xEE7003C0 /* MAC address high register */
301#define CXR25 0xEE7003C8 /* MAC address low register */
302int board_eth_init(bd_t *bis)
303{
304#ifdef CONFIG_SH_ETHER
305 int ret = -ENODEV;
306 u32 val;
307 unsigned char enetaddr[6];
308
309 ret = sh_eth_initialize(bis);
310 if (!eth_getenv_enetaddr("ethaddr", enetaddr))
311 return ret;
312
313 /* Set Mac address */
314 val = enetaddr[0] << 24 | enetaddr[1] << 16 |
315 enetaddr[2] << 8 | enetaddr[3];
316 writel(val, CXR24);
317
318 val = enetaddr[4] << 8 | enetaddr[5];
319 writel(val, CXR25);
320
321 return ret;
322#else
323 return 0;
324#endif
325}
326
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +0900327int dram_init(void)
328{
329 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
330 gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
331
332 return 0;
333}
334
Nobuhiro Iwamatsu90362c02013-10-20 20:37:17 +0900335/* koelsch has KSZ8041NL/RNL */
336#define PHY_CONTROL1 0x1E
337#define PHY_LED_MODE 0xC0000
338#define PHY_LED_MODE_ACK 0x4000
339int board_phy_config(struct phy_device *phydev)
340{
341 int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
342 ret &= ~PHY_LED_MODE;
343 ret |= PHY_LED_MODE_ACK;
344 ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
345
346 return 0;
347}
348
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +0900349const struct rmobile_sysinfo sysinfo = {
350 CONFIG_RMOBILE_BOARD_STRING
351};
352
353void dram_init_banksize(void)
354{
355 gd->bd->bi_dram[0].start = KOELSCH_SDRAM_BASE;
356 gd->bd->bi_dram[0].size = KOELSCH_SDRAM_SIZE;
357}
358
359int board_late_init(void)
360{
361 return 0;
362}
363
364void reset_cpu(ulong addr)
365{
Nobuhiro Iwamatsub8f383b2013-10-10 10:48:20 +0900366 u8 val;
367
368 i2c_set_bus_num(2); /* PowerIC connected to ch2 */
369 i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
370 val |= 0x02;
371 i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
Nobuhiro Iwamatsu1251e492013-11-21 17:07:46 +0900372}