arch/arm/dts/qcom-ipq4019.dtsi

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2019 Sartura Ltd.
 *
 * Author: Robert Marko <robert.marko@sartura.hr>
 */

 /dts-v1/;

#include "skeleton.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
#include <dt-bindings/clock/qcom,ipq4019-gcc.h>
#include <dt-bindings/reset/qcom,ipq4019-reset.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	model = "Qualcomm Technologies, Inc. IPQ4019";
	compatible = "qcom,ipq4019";

	aliases {
		serial0 = &blsp1_uart1;
	};

	reserved-memory {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		ranges;

		smem_mem: smem_region: smem@87e00000 {
			reg = <0x87e00000 0x080000>;
			no-map;
		};

		tz@87e80000 {
			reg = <0x87e80000 0x180000>;
			no-map;
		};
	};

	smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		gcc: clock-controller@1800000 {
			compatible = "qcom,gcc-ipq4019";
			reg = <0x1800000 0x60000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			u-boot,dm-pre-reloc;
		};

		reset: gcc-reset@1800000 {
			compatible = "qcom,gcc-reset-ipq4019";
			reg = <0x1800000 0x60000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			u-boot,dm-pre-reloc;
		};

		pinctrl: qcom,tlmm@1000000 {
			compatible = "qcom,tlmm-ipq4019";
			reg = <0x1000000 0x300000>;
			u-boot,dm-pre-reloc;
		};

		blsp1_uart1: serial@78af000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0x78af000 0x200>;
			clock = <&gcc GCC_BLSP1_UART1_APPS_CLK>;
			bit-rate = <0xFF>;
			status = "disabled";
			u-boot,dm-pre-reloc;
		};

		soc_gpios: pinctrl@1000000 {
			compatible = "qcom,ipq4019-pinctrl";
			reg = <0x1000000 0x300000>;
			gpio-controller;
			gpio-count = <100>;
			gpio-bank-name="soc";
			#gpio-cells = <2>;
		};

		usb3_ss_phy: ssphy@9a000 {
			compatible = "qcom,usb-ss-ipq4019-phy";
			#phy-cells = <0>;
			reg = <0x9a000 0x800>;
			reg-names = "phy_base";
			resets = <&reset USB3_UNIPHY_PHY_ARES>;
			reset-names = "por_rst";
			status = "disabled";
		};

		usb3_hs_phy: hsphy@a6000 {
			compatible = "qcom,usb-hs-ipq4019-phy";
			#phy-cells = <0>;
			reg = <0xa6000 0x40>;
			reg-names = "phy_base";
			resets = <&reset USB3_HSPHY_POR_ARES>, <&reset USB3_HSPHY_S_ARES>;
			reset-names = "por_rst", "srif_rst";
			status = "disabled";
		};

		usb3: usb3@8af8800 {
			compatible = "qcom,dwc3";
			reg = <0x8af8800 0x100>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&gcc GCC_USB3_MASTER_CLK>,
				 <&gcc GCC_USB3_SLEEP_CLK>,
				 <&gcc GCC_USB3_MOCK_UTMI_CLK>;
			clock-names = "master", "sleep", "mock_utmi";
			ranges;
			status = "disabled";

			dwc3@8a00000 {
				compatible = "snps,dwc3";
				reg = <0x8a00000 0xf8000>;
				phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
				phy-names = "usb2-phy", "usb3-phy";
				dr_mode = "host";
				maximum-speed = "super-speed";
				snps,dis_u2_susphy_quirk;
			};
		};

		usb2_hs_phy: hsphy@a8000 {
			compatible = "qcom,usb-hs-ipq4019-phy";
			#phy-cells = <0>;
			reg = <0xa8000 0x40>;
			reg-names = "phy_base";
			resets = <&reset USB2_HSPHY_POR_ARES>, <&reset USB2_HSPHY_S_ARES>;
			reset-names = "por_rst", "srif_rst";
			status = "disabled";
		};

		usb2: usb2@60f8800 {
			compatible = "qcom,dwc3";
			reg = <0x60f8800 0x100>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&gcc GCC_USB2_MASTER_CLK>,
				 <&gcc GCC_USB2_SLEEP_CLK>,
				 <&gcc GCC_USB2_MOCK_UTMI_CLK>;
			clock-names = "master", "sleep", "mock_utmi";
			ranges;
			status = "disabled";

			dwc3@6000000 {
				compatible = "snps,dwc3";
				reg = <0x6000000 0xf8000>;
				phys = <&usb2_hs_phy>;
				phy-names = "usb2-phy";
				dr_mode = "host";
				maximum-speed = "high-speed";
				snps,dis_u2_susphy_quirk;
			};
		};
	};
};