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Peter Pearse5ca98812007-11-09 15:24:26 +00001/*
2 * (C) Copyright 2005-2007
3 * Samsung Electronics,
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 *
6 * Configuration settings for the 2420 Samsung Apollon board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */
34#define CONFIG_OMAP 1 /* in a TI OMAP core */
35#define CONFIG_OMAP2420 1 /* which is in a 2420 */
36#define CONFIG_OMAP2420_APOLLON 1
37#define CONFIG_APOLLON 1
38#define CONFIG_APOLLON_PLUS 1 /* If you have apollon plus 1.x */
39
40/* Clock config to target*/
41#define PRCM_CONFIG_I 1
Wolfgang Denk435dc8f2008-01-09 11:36:21 +010042/* #define PRCM_CONFIG_II 1 */
Peter Pearse5ca98812007-11-09 15:24:26 +000043
44/* Boot method */
45/* uncomment if you use NOR boot */
Wolfgang Denk435dc8f2008-01-09 11:36:21 +010046/* #define CFG_NOR_BOOT 1 */
Peter Pearse5ca98812007-11-09 15:24:26 +000047
48/* uncomment if you use NOR on CS3 */
Wolfgang Denk435dc8f2008-01-09 11:36:21 +010049/* #define CFG_USE_NOR 1 */
Peter Pearse5ca98812007-11-09 15:24:26 +000050
51#ifdef CFG_NOR_BOOT
52#undef CFG_USE_NOR
53#define CFG_USE_NOR 1
54#endif
55
56#include <asm/arch/omap2420.h> /* get chip and board defs */
57
58#define V_SCLK 12000000
59
60/* input clock of PLL */
61/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
62#define CONFIG_SYS_CLK_FREQ V_SCLK
63
64#undef CONFIG_USE_IRQ /* no support for IRQs */
65#define CONFIG_MISC_INIT_R
66
67#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
68#define CONFIG_SETUP_MEMORY_TAGS 1
69#define CONFIG_INITRD_TAG 1
70#define CONFIG_REVISION_TAG 1
71
72/*
73 * Size of malloc() pool
74 */
75#define CFG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */
76#define CFG_MALLOC_LEN (CFG_ENV_SIZE + SZ_128K)
77#define CFG_GBL_DATA_SIZE 128 /* bytes reserved for initial data */
78
79/*
80 * Hardware drivers
81 */
82
83/*
84 * SMC91c96 Etherent
85 */
86#define CONFIG_DRIVER_LAN91C96
87#define CONFIG_LAN91C96_BASE (APOLLON_CS1_BASE+0x300)
88#define CONFIG_LAN91C96_EXT_PHY
89
90/*
91 * NS16550 Configuration
92 */
93#define V_NS16550_CLK (48000000) /* 48MHz (APLL96/2) */
94
95#define CFG_NS16550
96#define CFG_NS16550_SERIAL
97#define CFG_NS16550_REG_SIZE (-4)
98#define CFG_NS16550_CLK V_NS16550_CLK /* 3MHz (1.5MHz*2) */
99#define CFG_NS16550_COM1 OMAP2420_UART1
100
101/*
102 * select serial console configuration
103 */
104#define CONFIG_SERIAL1 1 /* UART1 on H4 */
105
106 /*
107 * I2C configuration
108 */
109#define CONFIG_HARD_I2C
110#define CFG_I2C_SPEED 100000
111#define CFG_I2C_SLAVE 1
112#define CONFIG_DRIVER_OMAP24XX_I2C
113
Wolfgang Denk435dc8f2008-01-09 11:36:21 +0100114/* allow to overwrite serial and ethaddr */
Peter Pearse5ca98812007-11-09 15:24:26 +0000115#define CONFIG_ENV_OVERWRITE
116#define CONFIG_CONS_INDEX 1
117#define CONFIG_BAUDRATE 115200
118#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
119
Wolfgang Denk435dc8f2008-01-09 11:36:21 +0100120/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
Peter Pearse5ca98812007-11-09 15:24:26 +0000121#include <config_cmd_default.h>
122
123#define CONFIG_CMD_DHCP
124#define CONFIG_CMD_DIAG
125#define CONFIG_CMD_ONENAND
126
127#undef CONFIG_CMD_AUTOSCRIPT
128
129#ifndef CFG_USE_NOR
130# undef CONFIG_CMD_FLASH
131# undef CONFIG_CMD_IMLS
132#endif
133
134#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
135
136#define CONFIG_BOOTDELAY 1
137
138#define CONFIG_NETMASK 255.255.255.0
139#define CONFIG_IPADDR 192.168.116.25
140#define CONFIG_SERVERIP 192.168.116.1
141#define CONFIG_BOOTFILE "uImage"
142#define CONFIG_ETHADDR 00:0E:99:00:24:20
143
144#ifdef CONFIG_APOLLON_PLUS
145# define CONFIG_BOOTARGS "root=/dev/nfs rw mem=64M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
146#else
147# define CONFIG_BOOTARGS "root=/dev/nfs rw mem=128M console=ttyS0,115200n8 ip=192.168.116.25:192.168.116.1:192.168.116.1:255.255.255.0:apollon:eth0:off nfsroot=/tftpboot/nfsroot profile=2"
148#endif
149
150#define CONFIG_EXTRA_ENV_SETTINGS \
Peter Pearse2ae64f52007-11-15 08:58:00 +0000151 "Image=tftp 0x80008000 Image; go 0x80008000\0" \
152 "zImage=tftp 0x80180000 zImage; go 0x80180000\0" \
153 "uImage=tftp 0x80180000 uImage; bootm 0x80180000\0" \
154 "uboot=tftp 0x80008000 u-boot.bin; go 0x80008000\0" \
155 "xloader=tftp 0x80180000 x-load.bin; cp.w 0x80180000 0x00000400 0x1000; go 0x00000400\0" \
156 "syncmode50=mw.w 0x1e442 0xc0c4; mw 0x6800a060 0xe30d1201\0" \
157 "syncmode=mw.w 0x1e442 0xe0f4; mw 0x6800a060 0xe30d1201\0" \
158 "norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \
159 "oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\
Peter Pearse5ca98812007-11-09 15:24:26 +0000160 "onesyncboot=run syncmode oneboot\0" \
161 "bootcmd=run uboot\0"
162
163/*
164 * Miscellaneous configurable options
165 */
166#define V_PROMPT "Apollon # "
167
168#define CFG_LONGHELP /* undef to save memory */
169#define CFG_PROMPT V_PROMPT
170#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
171/* Print Buffer Size */
172#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
173#define CFG_MAXARGS 16 /* max number of command args */
174#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
175
176#define CFG_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */
177#define CFG_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M)
178
179#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
180
181#define CFG_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */
182
Wolfgang Denk435dc8f2008-01-09 11:36:21 +0100183/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2)
184 * or by 32KHz clk, or from external sig. This rate is divided by a local
Peter Pearse5ca98812007-11-09 15:24:26 +0000185 * divisor.
186 */
187#define V_PVT 7 /* use with 12MHz/128 */
188
189#define CFG_TIMERBASE OMAP2420_GPT2
190#define CFG_PVT V_PVT /* 2^(pvt+1) */
191#define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
192
193/*-----------------------------------------------------------------------
194 * Stack sizes
195 *
Wolfgang Denk435dc8f2008-01-09 11:36:21 +0100196 * The stack sizes are set up in start.S using the settings below
Peter Pearse5ca98812007-11-09 15:24:26 +0000197 */
198#define CONFIG_STACKSIZE SZ_128K /* regular stack */
199#ifdef CONFIG_USE_IRQ
200# define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */
201# define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */
202#endif
203
204/*-----------------------------------------------------------------------
205 * Physical Memory Map
206 */
207#define CONFIG_NR_DRAM_BANKS 1 /* CS1 may or may not be populated */
208#define PHYS_SDRAM_1 OMAP2420_SDRC_CS0
209#define PHYS_SDRAM_1_SIZE SZ_128M
210#define PHYS_SDRAM_2 OMAP2420_SDRC_CS1
211
212/*-----------------------------------------------------------------------
213 * FLASH and environment organization
214 */
215#ifdef CFG_USE_NOR
216/* OneNAND boot, NOR has CS3, But NOR has CS0 when NOR boot */
217# define CFG_FLASH_BASE 0x18000000
218# define CFG_MAX_FLASH_BANKS 1
219# define CFG_MAX_FLASH_SECT 1024
220/*-----------------------------------------------------------------------
221
222 * CFI FLASH driver setup
223 */
224# define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */
225# define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */
Wolfgang Denk435dc8f2008-01-09 11:36:21 +0100226/* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* Use buffered writes (~10x faster) */
Peter Pearse5ca98812007-11-09 15:24:26 +0000227# define CFG_FLASH_PROTECTION 1 /* Use h/w sector protection*/
228
229#else /* !CFG_USE_NOR */
230# define CFG_NO_FLASH 1
231#endif /* CFG_USE_NOR */
232
233/* OneNAND boot, OneNAND has CS0, NOR boot ONeNAND has CS2 */
234#define CFG_ONENAND_BASE 0x00000000
235#define CFG_ENV_IS_IN_ONENAND 1
236#define CFG_ENV_ADDR 0x00020000
237
238#endif /* __CONFIG_H */