blob: 6516a727642f3afaad3c8c04249e75d1eabbcdf2 [file] [log] [blame]
Akshay Saraswat8e4ab1d2014-06-18 17:53:58 +05301/*
2 * Copyright (C) 2013 Samsung Electronics
3 *
4 * Configuration settings for the SAMSUNG/GOOGLE PEACH-PIT board.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_PEACH_PIT_H
10#define __CONFIG_PEACH_PIT_H
11
Simon Glassf94de732014-10-07 22:01:48 -060012#define CONFIG_ENV_IS_IN_SPI_FLASH
13#define CONFIG_SPI_FLASH
14#define CONFIG_ENV_SPI_BASE 0x12D30000
15#define FLASH_SIZE (0x4 << 20)
16#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE)
Hyungwon Hwang43900da2014-12-12 14:45:44 +090017#define CONFIG_SPI_BOOTING
Simon Glassf94de732014-10-07 22:01:48 -060018
Simon Glass87033d42014-10-07 22:01:46 -060019#include <configs/exynos5420-common.h>
Simon Glass7d159532014-10-07 22:01:47 -060020#include <configs/exynos5-dt-common.h>
Akshay Saraswat8e4ab1d2014-06-18 17:53:58 +053021
Simon Glassf94de732014-10-07 22:01:48 -060022#define CONFIG_BOARD_COMMON
Akshay Saraswat8e4ab1d2014-06-18 17:53:58 +053023
Hyungwon Hwang43900da2014-12-12 14:45:44 +090024#define CONFIG_SYS_SDRAM_BASE 0x20000000
25#define CONFIG_SYS_TEXT_BASE 0x23E00000
26#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
27
Akshay Saraswat8e4ab1d2014-06-18 17:53:58 +053028/* select serial console configuration */
29#define CONFIG_SERIAL3 /* use SERIAL 3 */
Hyungwon Hwang43900da2014-12-12 14:45:44 +090030#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
Akshay Saraswat8e4ab1d2014-06-18 17:53:58 +053031
Akshay Saraswat79043d82014-11-13 22:38:17 +053032#define CONFIG_SYS_PROMPT "Peach-Pit # "
33#define CONFIG_IDENT_STRING " for Peach-Pit"
Akshay Saraswat8e4ab1d2014-06-18 17:53:58 +053034
Ajay Kumar5cecf212014-09-05 16:53:38 +053035#define CONFIG_VIDEO_PARADE
36
37/* Display */
38#define CONFIG_LCD
39#ifdef CONFIG_LCD
40#define CONFIG_EXYNOS_FB
41#define CONFIG_EXYNOS_DP
42#define LCD_BPP LCD_COLOR16
43#endif
44
Simon Glass5b9c8cb2014-10-07 22:01:41 -060045#define CONFIG_POWER_TPS65090_EC
Simon Glass98149d72014-10-07 22:01:42 -060046#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */
Simon Glassea0ebc82014-10-13 23:42:16 -060047#define CONFIG_DM_CROS_EC
Simon Glass5b9c8cb2014-10-07 22:01:41 -060048
Simon Glassf94de732014-10-07 22:01:48 -060049#define CONFIG_USB_XHCI
50#define CONFIG_USB_XHCI_EXYNOS
51
Akshay Saraswat43581c82014-11-13 22:38:19 +053052/* DRAM Memory Banks */
53#define CONFIG_NR_DRAM_BANKS 4
54#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
55
Akshay Saraswat8e4ab1d2014-06-18 17:53:58 +053056#endif /* __CONFIG_PEACH_PIT_H */