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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Scott Wood96b8a052007-04-16 14:54:15 -05002/*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4 *
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
Scott Wood96b8a052007-04-16 14:54:15 -05008 */
9
10#include <common.h>
11#include <mpc83xx.h>
12#include <spd_sdram.h>
13
14#include <asm/bitops.h>
15#include <asm/io.h>
16
17#include <asm/processor.h>
18
Wolfgang Denk1218abf2007-09-15 20:48:41 +020019DECLARE_GLOBAL_DATA_PTR;
20
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020021#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -050022static void resume_from_sleep(void)
23{
Scott Wood96b8a052007-04-16 14:54:15 -050024 u32 magic = *(u32 *)0;
25
26 typedef void (*func_t)(void);
27 func_t resume = *(func_t *)4;
28
29 if (magic == 0xf5153ae5)
30 resume();
31
32 gd->flags &= ~GD_FLG_SILENT;
33 puts("\nResume from sleep failed: bad magic word\n");
34}
35#endif
36
37/* Fixed sdram init -- doesn't use serial presence detect.
38 *
39 * This is useful for faster booting in configs where the RAM is unlikely
40 * to be changed, or for things like NAND booting where space is tight.
41 */
42static long fixed_sdram(void)
43{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
Scott Woode4c09502008-06-30 14:13:28 -050045
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#ifndef CONFIG_SYS_RAMBOOT
47 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Scott Wood96b8a052007-04-16 14:54:15 -050048 u32 msize_log2 = __ilog2(msize);
49
Mario Six133ec602019-01-21 09:18:16 +010050 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
Scott Wood96b8a052007-04-16 14:54:15 -050051 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
Scott Wood96b8a052007-04-16 14:54:15 -050053
54 /*
55 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
56 * or the DDR2 controller may fail to initialize correctly.
57 */
Ingo van Lil3eb90ba2009-11-24 14:09:21 +010058 __udelay(50000);
Scott Wood96b8a052007-04-16 14:54:15 -050059
Mario Six133ec602019-01-21 09:18:16 +010060#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
Joe Hershberger2e651b22011-10-11 23:57:31 -050061#warning Chip select bounds is only configurable in 16MB increments
62#endif
63 im->ddr.csbnds[0].csbnds =
Mario Six133ec602019-01-21 09:18:16 +010064 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
65 (((CONFIG_SYS_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
Joe Hershberger2e651b22011-10-11 23:57:31 -050066 CSBNDS_EA);
67 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
Scott Wood96b8a052007-04-16 14:54:15 -050068
69 /* Currently we use only one CS, so disable the other bank. */
70 im->ddr.cs_config[1] = 0;
71
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
73 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
76 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
Scott Wood96b8a052007-04-16 14:54:15 -050077
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -050079 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
Scott Wood96b8a052007-04-16 14:54:15 -050081 else
82#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083 im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
Scott Wood96b8a052007-04-16 14:54:15 -050084
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
86 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
87 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
Scott Wood96b8a052007-04-16 14:54:15 -050088
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Scott Wood96b8a052007-04-16 14:54:15 -050090 sync();
91
92 /* enable DDR controller */
93 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
Scott Woode4c09502008-06-30 14:13:28 -050094#endif
Scott Wood96b8a052007-04-16 14:54:15 -050095
96 return msize;
97}
98
Simon Glassf1683aa2017-04-06 12:47:05 -060099int dram_init(void)
Scott Wood96b8a052007-04-16 14:54:15 -0500100{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500102 volatile fsl_lbc_t *lbc = &im->im_lbc;
Scott Wood96b8a052007-04-16 14:54:15 -0500103 u32 msize;
104
105 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
Simon Glass088454c2017-03-31 08:40:25 -0600106 return -ENXIO;
Scott Wood96b8a052007-04-16 14:54:15 -0500107
Scott Wood96b8a052007-04-16 14:54:15 -0500108 /* DDR SDRAM - Main SODIMM */
109 msize = fixed_sdram();
110
111 /* Local Bus setup lbcr and mrtpr */
Mario Six42c9a492019-01-21 09:18:17 +0100112 lbc->lbcr = (0x00040000 | (0xFF << LBCR_BMT_SHIFT) | 0xF);
113 /* LB refresh timer prescal, 266MHz/32 */
114 lbc->mrtpr = 0x20000000;
Scott Wood96b8a052007-04-16 14:54:15 -0500115 sync();
116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
Scott Wood96b8a052007-04-16 14:54:15 -0500118 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
119 resume_from_sleep();
120#endif
121
Scott Wood96b8a052007-04-16 14:54:15 -0500122 /* return total bus SDRAM size(bytes) -- DDR */
Simon Glass088454c2017-03-31 08:40:25 -0600123 gd->ram_size = msize;
124
125 return 0;
Scott Wood96b8a052007-04-16 14:54:15 -0500126}