Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 |
| 4 | * David Feng <fenghua@phytium.com.cn> |
| 5 | * Sharma Bhupesh <bhupesh.sharma@freescale.com> |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 6 | */ |
| 7 | #include <common.h> |
Simon Glass | 9a3b4ce | 2019-12-28 10:45:01 -0700 | [diff] [blame] | 8 | #include <cpu_func.h> |
Simon Glass | 9d92245 | 2017-05-17 17:18:03 -0600 | [diff] [blame] | 9 | #include <dm.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 10 | #include <init.h> |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 11 | #include <malloc.h> |
| 12 | #include <errno.h> |
Simon Glass | 90526e9 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 13 | #include <net.h> |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 14 | #include <netdev.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 15 | #include <asm/global_data.h> |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 16 | #include <asm/io.h> |
| 17 | #include <linux/compiler.h> |
David Feng | d8bafe13 | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 18 | #include <dm/platform_data/serial_pl01x.h> |
Liviu Dudau | 2fdc9b7 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 19 | #include "pcie.h" |
Alexander Graf | e593bf5 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 20 | #include <asm/armv8/mmu.h> |
Peter Hoyes | 439581d | 2021-11-11 09:26:03 +0000 | [diff] [blame^] | 21 | #ifdef CONFIG_VIRTIO_NET |
| 22 | #include <virtio_types.h> |
| 23 | #include <virtio.h> |
| 24 | #endif |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 25 | |
| 26 | DECLARE_GLOBAL_DATA_PTR; |
| 27 | |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 28 | static const struct pl01x_serial_plat serial_plat = { |
David Feng | d8bafe13 | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 29 | .base = V2M_UART0, |
| 30 | .type = TYPE_PL011, |
Linus Walleij | d280ea0 | 2015-04-14 10:01:35 +0200 | [diff] [blame] | 31 | .clock = CONFIG_PL011_CLOCK, |
David Feng | d8bafe13 | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 32 | }; |
| 33 | |
Simon Glass | 20e442a | 2020-12-28 20:34:54 -0700 | [diff] [blame] | 34 | U_BOOT_DRVINFO(vexpress_serials) = { |
David Feng | d8bafe13 | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 35 | .name = "serial_pl01x", |
Simon Glass | 8a8d24b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 36 | .plat = &serial_plat, |
David Feng | d8bafe13 | 2015-01-31 11:55:29 +0800 | [diff] [blame] | 37 | }; |
| 38 | |
Alexander Graf | e593bf5 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 39 | static struct mm_region vexpress64_mem_map[] = { |
| 40 | { |
York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 41 | .virt = 0x0UL, |
| 42 | .phys = 0x0UL, |
Alexander Graf | e593bf5 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 43 | .size = 0x80000000UL, |
| 44 | .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| 45 | PTE_BLOCK_NON_SHARE | |
| 46 | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| 47 | }, { |
York Sun | cd4b0c5 | 2016-06-24 16:46:22 -0700 | [diff] [blame] | 48 | .virt = 0x80000000UL, |
| 49 | .phys = 0x80000000UL, |
Alexander Graf | e593bf5 | 2016-03-04 01:09:51 +0100 | [diff] [blame] | 50 | .size = 0xff80000000UL, |
| 51 | .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| 52 | PTE_BLOCK_INNER_SHARE |
| 53 | }, { |
| 54 | /* List terminator */ |
| 55 | 0, |
| 56 | } |
| 57 | }; |
| 58 | |
| 59 | struct mm_region *mem_map = vexpress64_mem_map; |
| 60 | |
Ryan Harkin | bc8d3bc | 2015-11-18 10:39:06 +0000 | [diff] [blame] | 61 | /* This function gets replaced by platforms supporting PCIe. |
| 62 | * The replacement function, eg. on Juno, initialises the PCIe bus. |
| 63 | */ |
| 64 | __weak void vexpress64_pcie_init(void) |
| 65 | { |
| 66 | } |
| 67 | |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 68 | int board_init(void) |
| 69 | { |
Liviu Dudau | 2fdc9b7 | 2015-10-19 11:08:32 +0100 | [diff] [blame] | 70 | vexpress64_pcie_init(); |
Peter Hoyes | 439581d | 2021-11-11 09:26:03 +0000 | [diff] [blame^] | 71 | #ifdef CONFIG_VIRTIO_NET |
| 72 | virtio_init(); |
| 73 | #endif |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | int dram_init(void) |
| 78 | { |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 79 | gd->ram_size = PHYS_SDRAM_1_SIZE; |
| 80 | return 0; |
| 81 | } |
| 82 | |
Simon Glass | 76b00ac | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 83 | int dram_init_banksize(void) |
Liviu Dudau | 2d0cee1 | 2015-10-19 11:08:31 +0100 | [diff] [blame] | 84 | { |
| 85 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; |
| 86 | gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; |
Ryan Harkin | 2c2b218 | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 87 | #ifdef PHYS_SDRAM_2 |
Liviu Dudau | 2d0cee1 | 2015-10-19 11:08:31 +0100 | [diff] [blame] | 88 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; |
| 89 | gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; |
Ryan Harkin | 2c2b218 | 2015-11-18 10:39:07 +0000 | [diff] [blame] | 90 | #endif |
Simon Glass | 76b00ac | 2017-03-31 08:40:32 -0600 | [diff] [blame] | 91 | |
| 92 | return 0; |
Liviu Dudau | 2d0cee1 | 2015-10-19 11:08:31 +0100 | [diff] [blame] | 93 | } |
| 94 | |
Peter Hoyes | 2661397 | 2021-11-11 09:26:02 +0000 | [diff] [blame] | 95 | /* Assigned in lowlevel_init.S |
| 96 | * Push the variable into the .data section so that it |
| 97 | * does not get cleared later. |
| 98 | */ |
| 99 | unsigned long __section(".data") prior_stage_fdt_address; |
| 100 | |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 101 | #ifdef CONFIG_OF_BOARD |
Peter Hoyes | 2661397 | 2021-11-11 09:26:02 +0000 | [diff] [blame] | 102 | |
| 103 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 104 | #define JUNO_FLASH_SEC_SIZE (256 * 1024) |
| 105 | static phys_addr_t find_dtb_in_nor_flash(const char *partname) |
| 106 | { |
| 107 | phys_addr_t sector = CONFIG_SYS_FLASH_BASE; |
| 108 | int i; |
| 109 | |
| 110 | for (i = 0; |
| 111 | i < CONFIG_SYS_MAX_FLASH_SECT; |
| 112 | i++, sector += JUNO_FLASH_SEC_SIZE) { |
| 113 | int len = strlen(partname) + 1; |
| 114 | int offs; |
| 115 | phys_addr_t imginfo; |
| 116 | u32 reg; |
| 117 | |
| 118 | reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04); |
| 119 | /* This makes up the string "HSLFTOOF" flash footer */ |
| 120 | if (reg != 0x464F4F54U) |
| 121 | continue; |
| 122 | reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08); |
| 123 | if (reg != 0x464C5348U) |
| 124 | continue; |
| 125 | |
| 126 | for (offs = 0; offs < 32; offs += 4, len -= 4) { |
| 127 | reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs); |
| 128 | if (strncmp(partname + offs, (char *)®, |
| 129 | len > 4 ? 4 : len)) |
| 130 | break; |
| 131 | |
| 132 | if (len > 4) |
| 133 | continue; |
| 134 | |
| 135 | reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10); |
| 136 | imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg; |
| 137 | reg = readl(imginfo + 0x54); |
| 138 | |
| 139 | return CONFIG_SYS_FLASH_BASE + |
| 140 | reg * JUNO_FLASH_SEC_SIZE; |
| 141 | } |
| 142 | } |
| 143 | |
| 144 | printf("No DTB found\n"); |
| 145 | |
| 146 | return ~0; |
| 147 | } |
Peter Hoyes | 2661397 | 2021-11-11 09:26:02 +0000 | [diff] [blame] | 148 | #endif |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 149 | |
Ilias Apalodimas | e7fb789 | 2021-10-26 09:12:33 +0300 | [diff] [blame] | 150 | void *board_fdt_blob_setup(int *err) |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 151 | { |
Peter Hoyes | 2661397 | 2021-11-11 09:26:02 +0000 | [diff] [blame] | 152 | #ifdef CONFIG_TARGET_VEXPRESS64_JUNO |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 153 | phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART); |
| 154 | |
Ilias Apalodimas | e7fb789 | 2021-10-26 09:12:33 +0300 | [diff] [blame] | 155 | *err = 0; |
| 156 | if (fdt_rom_addr == ~0UL) { |
| 157 | *err = -ENXIO; |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 158 | return NULL; |
Ilias Apalodimas | e7fb789 | 2021-10-26 09:12:33 +0300 | [diff] [blame] | 159 | } |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 160 | |
| 161 | return (void *)fdt_rom_addr; |
Peter Hoyes | 2661397 | 2021-11-11 09:26:02 +0000 | [diff] [blame] | 162 | #endif |
| 163 | |
| 164 | #ifdef VEXPRESS_FDT_ADDR |
| 165 | if (fdt_magic(VEXPRESS_FDT_ADDR) == FDT_MAGIC) { |
| 166 | *err = 0; |
| 167 | return (void *)VEXPRESS_FDT_ADDR; |
| 168 | } |
| 169 | #endif |
| 170 | |
| 171 | if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC) { |
| 172 | *err = 0; |
| 173 | return (void *)prior_stage_fdt_address; |
| 174 | } |
| 175 | |
| 176 | *err = -ENXIO; |
| 177 | return NULL; |
Andre Przywara | b3270e9 | 2020-04-27 19:18:01 +0100 | [diff] [blame] | 178 | } |
| 179 | #endif |
| 180 | |
Andre Przywara | be0d096 | 2020-04-27 19:18:02 +0100 | [diff] [blame] | 181 | /* Actual reset is done via PSCI. */ |
Harald Seiler | 35b65dd | 2020-12-15 16:47:52 +0100 | [diff] [blame] | 182 | void reset_cpu(void) |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 183 | { |
| 184 | } |
| 185 | |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 186 | /* |
| 187 | * Board specific ethernet initialization routine. |
| 188 | */ |
Masahiro Yamada | b75d8dc | 2020-06-26 15:13:33 +0900 | [diff] [blame] | 189 | int board_eth_init(struct bd_info *bis) |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 190 | { |
| 191 | int rc = 0; |
Andre Przywara | cc696e7 | 2020-06-11 12:03:18 +0100 | [diff] [blame] | 192 | #ifndef CONFIG_DM_ETH |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 193 | #ifdef CONFIG_SMC91111 |
| 194 | rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); |
| 195 | #endif |
Linus Walleij | b31f9d7 | 2015-02-17 11:35:25 +0100 | [diff] [blame] | 196 | #ifdef CONFIG_SMC911X |
| 197 | rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); |
| 198 | #endif |
Andre Przywara | cc696e7 | 2020-06-11 12:03:18 +0100 | [diff] [blame] | 199 | #endif |
David Feng | 1291682 | 2013-12-14 11:47:37 +0800 | [diff] [blame] | 200 | return rc; |
| 201 | } |