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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
David Feng12916822013-12-14 11:47:37 +08002/*
3 * (C) Copyright 2013
4 * David Feng <fenghua@phytium.com.cn>
5 * Sharma Bhupesh <bhupesh.sharma@freescale.com>
David Feng12916822013-12-14 11:47:37 +08006 */
7#include <common.h>
Simon Glass9a3b4ce2019-12-28 10:45:01 -07008#include <cpu_func.h>
Simon Glass9d922452017-05-17 17:18:03 -06009#include <dm.h>
Simon Glass691d7192020-05-10 11:40:02 -060010#include <init.h>
David Feng12916822013-12-14 11:47:37 +080011#include <malloc.h>
12#include <errno.h>
Simon Glass90526e92020-05-10 11:39:56 -060013#include <net.h>
David Feng12916822013-12-14 11:47:37 +080014#include <netdev.h>
Simon Glass401d1c42020-10-30 21:38:53 -060015#include <asm/global_data.h>
David Feng12916822013-12-14 11:47:37 +080016#include <asm/io.h>
17#include <linux/compiler.h>
David Fengd8bafe132015-01-31 11:55:29 +080018#include <dm/platform_data/serial_pl01x.h>
Liviu Dudau2fdc9b72015-10-19 11:08:32 +010019#include "pcie.h"
Alexander Grafe593bf52016-03-04 01:09:51 +010020#include <asm/armv8/mmu.h>
Peter Hoyes439581d2021-11-11 09:26:03 +000021#ifdef CONFIG_VIRTIO_NET
22#include <virtio_types.h>
23#include <virtio.h>
24#endif
David Feng12916822013-12-14 11:47:37 +080025
26DECLARE_GLOBAL_DATA_PTR;
27
Simon Glass8a8d24b2020-12-03 16:55:23 -070028static const struct pl01x_serial_plat serial_plat = {
David Fengd8bafe132015-01-31 11:55:29 +080029 .base = V2M_UART0,
30 .type = TYPE_PL011,
Linus Walleijd280ea02015-04-14 10:01:35 +020031 .clock = CONFIG_PL011_CLOCK,
David Fengd8bafe132015-01-31 11:55:29 +080032};
33
Simon Glass20e442a2020-12-28 20:34:54 -070034U_BOOT_DRVINFO(vexpress_serials) = {
David Fengd8bafe132015-01-31 11:55:29 +080035 .name = "serial_pl01x",
Simon Glass8a8d24b2020-12-03 16:55:23 -070036 .plat = &serial_plat,
David Fengd8bafe132015-01-31 11:55:29 +080037};
38
Alexander Grafe593bf52016-03-04 01:09:51 +010039static struct mm_region vexpress64_mem_map[] = {
40 {
York Suncd4b0c52016-06-24 16:46:22 -070041 .virt = 0x0UL,
42 .phys = 0x0UL,
Alexander Grafe593bf52016-03-04 01:09:51 +010043 .size = 0x80000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
45 PTE_BLOCK_NON_SHARE |
46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
47 }, {
York Suncd4b0c52016-06-24 16:46:22 -070048 .virt = 0x80000000UL,
49 .phys = 0x80000000UL,
Alexander Grafe593bf52016-03-04 01:09:51 +010050 .size = 0xff80000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
52 PTE_BLOCK_INNER_SHARE
53 }, {
54 /* List terminator */
55 0,
56 }
57};
58
59struct mm_region *mem_map = vexpress64_mem_map;
60
Ryan Harkinbc8d3bc2015-11-18 10:39:06 +000061/* This function gets replaced by platforms supporting PCIe.
62 * The replacement function, eg. on Juno, initialises the PCIe bus.
63 */
64__weak void vexpress64_pcie_init(void)
65{
66}
67
David Feng12916822013-12-14 11:47:37 +080068int board_init(void)
69{
Liviu Dudau2fdc9b72015-10-19 11:08:32 +010070 vexpress64_pcie_init();
Peter Hoyes439581d2021-11-11 09:26:03 +000071#ifdef CONFIG_VIRTIO_NET
72 virtio_init();
73#endif
David Feng12916822013-12-14 11:47:37 +080074 return 0;
75}
76
77int dram_init(void)
78{
David Feng12916822013-12-14 11:47:37 +080079 gd->ram_size = PHYS_SDRAM_1_SIZE;
80 return 0;
81}
82
Simon Glass76b00ac2017-03-31 08:40:32 -060083int dram_init_banksize(void)
Liviu Dudau2d0cee12015-10-19 11:08:31 +010084{
85 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
86 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
Ryan Harkin2c2b2182015-11-18 10:39:07 +000087#ifdef PHYS_SDRAM_2
Liviu Dudau2d0cee12015-10-19 11:08:31 +010088 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
89 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
Ryan Harkin2c2b2182015-11-18 10:39:07 +000090#endif
Simon Glass76b00ac2017-03-31 08:40:32 -060091
92 return 0;
Liviu Dudau2d0cee12015-10-19 11:08:31 +010093}
94
Peter Hoyes26613972021-11-11 09:26:02 +000095/* Assigned in lowlevel_init.S
96 * Push the variable into the .data section so that it
97 * does not get cleared later.
98 */
99unsigned long __section(".data") prior_stage_fdt_address;
100
Andre Przywarab3270e92020-04-27 19:18:01 +0100101#ifdef CONFIG_OF_BOARD
Peter Hoyes26613972021-11-11 09:26:02 +0000102
103#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarab3270e92020-04-27 19:18:01 +0100104#define JUNO_FLASH_SEC_SIZE (256 * 1024)
105static phys_addr_t find_dtb_in_nor_flash(const char *partname)
106{
107 phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
108 int i;
109
110 for (i = 0;
111 i < CONFIG_SYS_MAX_FLASH_SECT;
112 i++, sector += JUNO_FLASH_SEC_SIZE) {
113 int len = strlen(partname) + 1;
114 int offs;
115 phys_addr_t imginfo;
116 u32 reg;
117
118 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
119 /* This makes up the string "HSLFTOOF" flash footer */
120 if (reg != 0x464F4F54U)
121 continue;
122 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
123 if (reg != 0x464C5348U)
124 continue;
125
126 for (offs = 0; offs < 32; offs += 4, len -= 4) {
127 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
128 if (strncmp(partname + offs, (char *)&reg,
129 len > 4 ? 4 : len))
130 break;
131
132 if (len > 4)
133 continue;
134
135 reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
136 imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
137 reg = readl(imginfo + 0x54);
138
139 return CONFIG_SYS_FLASH_BASE +
140 reg * JUNO_FLASH_SEC_SIZE;
141 }
142 }
143
144 printf("No DTB found\n");
145
146 return ~0;
147}
Peter Hoyes26613972021-11-11 09:26:02 +0000148#endif
Andre Przywarab3270e92020-04-27 19:18:01 +0100149
Ilias Apalodimase7fb7892021-10-26 09:12:33 +0300150void *board_fdt_blob_setup(int *err)
Andre Przywarab3270e92020-04-27 19:18:01 +0100151{
Peter Hoyes26613972021-11-11 09:26:02 +0000152#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarab3270e92020-04-27 19:18:01 +0100153 phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
154
Ilias Apalodimase7fb7892021-10-26 09:12:33 +0300155 *err = 0;
156 if (fdt_rom_addr == ~0UL) {
157 *err = -ENXIO;
Andre Przywarab3270e92020-04-27 19:18:01 +0100158 return NULL;
Ilias Apalodimase7fb7892021-10-26 09:12:33 +0300159 }
Andre Przywarab3270e92020-04-27 19:18:01 +0100160
161 return (void *)fdt_rom_addr;
Peter Hoyes26613972021-11-11 09:26:02 +0000162#endif
163
164#ifdef VEXPRESS_FDT_ADDR
165 if (fdt_magic(VEXPRESS_FDT_ADDR) == FDT_MAGIC) {
166 *err = 0;
167 return (void *)VEXPRESS_FDT_ADDR;
168 }
169#endif
170
171 if (fdt_magic(prior_stage_fdt_address) == FDT_MAGIC) {
172 *err = 0;
173 return (void *)prior_stage_fdt_address;
174 }
175
176 *err = -ENXIO;
177 return NULL;
Andre Przywarab3270e92020-04-27 19:18:01 +0100178}
179#endif
180
Andre Przywarabe0d0962020-04-27 19:18:02 +0100181/* Actual reset is done via PSCI. */
Harald Seiler35b65dd2020-12-15 16:47:52 +0100182void reset_cpu(void)
David Feng12916822013-12-14 11:47:37 +0800183{
184}
185
David Feng12916822013-12-14 11:47:37 +0800186/*
187 * Board specific ethernet initialization routine.
188 */
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900189int board_eth_init(struct bd_info *bis)
David Feng12916822013-12-14 11:47:37 +0800190{
191 int rc = 0;
Andre Przywaracc696e72020-06-11 12:03:18 +0100192#ifndef CONFIG_DM_ETH
David Feng12916822013-12-14 11:47:37 +0800193#ifdef CONFIG_SMC91111
194 rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
195#endif
Linus Walleijb31f9d72015-02-17 11:35:25 +0100196#ifdef CONFIG_SMC911X
197 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
198#endif
Andre Przywaracc696e72020-06-11 12:03:18 +0100199#endif
David Feng12916822013-12-14 11:47:37 +0800200 return rc;
201}