blob: 7f5a36f1ebffab505fa38fea4f9764a3391ec3b0 [file] [log] [blame]
Kyle Moffettf8bbb4d2011-12-07 16:39:16 -05001/*
2 * Copyright 2009-2010 eXMeritus, A Boeing Company
3 * Copyright 2008-2009 Freescale Semiconductor, Inc.
4 *
5 * (C) Copyright 2000
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Kyle Moffettf8bbb4d2011-12-07 16:39:16 -05009 */
10
11#include <common.h>
12#include <asm/mmu.h>
13
14struct fsl_e_tlb_entry tlb_table[] = {
15 /* TLB 0 - for temp stack in cache */
16 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 0 * 1024,
17 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 0 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20
21 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
22 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
23 MAS3_SX|MAS3_SW|MAS3_SR, 0,
24 0, 0, BOOKE_PAGESZ_4K, 0),
25
26 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
27 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
28 MAS3_SX|MAS3_SW|MAS3_SR, 0,
29 0, 0, BOOKE_PAGESZ_4K, 0),
30
31 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
32 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
33 MAS3_SX|MAS3_SW|MAS3_SR, 0,
34 0, 0, BOOKE_PAGESZ_4K, 0),
35
36 /* TLB 1 */
37 /* *I*** - Boot page */
38 SET_TLB_ENTRY(1, CONFIG_BPTR_VIRT_ADDR,
39 CONFIG_BPTR_VIRT_ADDR,
40 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41 0, 0, BOOKE_PAGESZ_4K, 1),
42
43 /* *I*G* - CCSRBAR */
44 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR,
45 CONFIG_SYS_CCSRBAR_PHYS,
46 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
47 0, 1, BOOKE_PAGESZ_1M, 1),
48
49 /*
50 * W**G* - FLASH (Will be *I*G* after relocation to RAM)
51 *
52 * This maps both SPI FLASH chips (128MByte per chip)
53 */
54 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,
55 CONFIG_SYS_FLASH_BASE_PHYS,
56 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
57 0, 2, BOOKE_PAGESZ_256M, 1),
58
59 /*
60 * *I*G* - PCI memory
61 *
62 * We have 1.5GB total PCI-E memory space to map and we want to use
63 * the minimum possible number of TLB entries. Since Book-E TLB
64 * entries are sized in powers of 4, we use 1GB + 256MB + 256MB.
65 */
66 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT,
67 CONFIG_SYS_PCIE3_MEM_PHYS,
68 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
69 0, 3, BOOKE_PAGESZ_1G, 1),
70 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
71 CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
72 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 4, BOOKE_PAGESZ_256M, 1),
74 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
75 CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
76 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
77 0, 5, BOOKE_PAGESZ_256M, 1),
78
79 /*
80 * *I*G* - PCI I/O
81 *
82 * This one entry covers all 3 64k PCI-E I/O windows
83 */
84 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT,
85 CONFIG_SYS_PCIE3_IO_PHYS,
86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 0, 6, BOOKE_PAGESZ_256K, 1),
88};
89
90int num_tlb_entries = ARRAY_SIZE(tlb_table);