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wdenkc0218802003-03-27 12:09:35 +00001/*
2 * Memory sub-system initialization code for INCA-IP development board.
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkd4ca31c2004-01-02 14:00:00 +000016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc0218802003-03-27 12:09:35 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/regdef.h>
28
29
wdenkd4ca31c2004-01-02 14:00:00 +000030#define EBU_MODUL_BASE 0xB8000200
31#define EBU_CLC(value) 0x0000(value)
32#define EBU_CON(value) 0x0010(value)
33#define EBU_ADDSEL0(value) 0x0020(value)
34#define EBU_ADDSEL1(value) 0x0024(value)
35#define EBU_ADDSEL2(value) 0x0028(value)
36#define EBU_BUSCON0(value) 0x0060(value)
37#define EBU_BUSCON1(value) 0x0064(value)
38#define EBU_BUSCON2(value) 0x0068(value)
wdenkc0218802003-03-27 12:09:35 +000039
wdenkd4ca31c2004-01-02 14:00:00 +000040#define MC_MODUL_BASE 0xBF800000
41#define MC_ERRCAUSE(value) 0x0100(value)
42#define MC_ERRADDR(value) 0x0108(value)
43#define MC_IOGP(value) 0x0800(value)
44#define MC_SELFRFSH(value) 0x0A00(value)
45#define MC_CTRLENA(value) 0x1000(value)
46#define MC_MRSCODE(value) 0x1008(value)
47#define MC_CFGDW(value) 0x1010(value)
48#define MC_CFGPB0(value) 0x1018(value)
49#define MC_LATENCY(value) 0x1038(value)
50#define MC_TREFRESH(value) 0x1040(value)
wdenkc0218802003-03-27 12:09:35 +000051
wdenkd4ca31c2004-01-02 14:00:00 +000052#define CGU_MODUL_BASE 0xBF107000
53#define CGU_PLL1CR(value) 0x0008(value)
54#define CGU_DIVCR(value) 0x0010(value)
55#define CGU_MUXCR(value) 0x0014(value)
56#define CGU_PLL1SR(value) 0x000C(value)
wdenkc0218802003-03-27 12:09:35 +000057
wdenkd4ca31c2004-01-02 14:00:00 +000058 .set noreorder
wdenk7cb22f92003-12-27 19:24:54 +000059
60
61/*
62 * void ebu_init(long)
63 *
64 * a0 has the clock value we are going to run at
65 */
66 .globl ebu_init
67 .ent ebu_init
68ebu_init:
Wolfgang Denkf013dac2005-12-04 00:40:34 +010069__ebu_init:
wdenk7cb22f92003-12-27 19:24:54 +000070
71 li t1, EBU_MODUL_BASE
72 li t2, 0xA0000041
73 sw t2, EBU_ADDSEL0(t1)
74 li t2, 0xA0800041
75 sw t2, EBU_ADDSEL2(t1)
76 li t2, 0xBE0000F1
77 sw t2, EBU_ADDSEL1(t1)
78
79 li t3, 100000000
80 beq a0, t3, 1f
81 nop
82 li t3, 133000000
83 beq a0, t3, 2f
84 nop
85 li t3, 150000000
86 beq a0, t3, 2f
87 nop
88 b 3f
89 nop
90
91 /* 100 MHz */
921:
93 li t2, 0x8841417D
94 sw t2, EBU_BUSCON0(t1)
95 sw t2, EBU_BUSCON2(t1)
96 li t2, 0x684142BD
97 b 3f
98 sw t2, EBU_BUSCON1(t1) /* delay slot */
99
100 /* 133 or 150 MHz */
1012:
102 li t2, 0x8841417E
103 sw t2, EBU_BUSCON0(t1)
104 sw t2, EBU_BUSCON2(t1)
105 li t2, 0x684143FD
106 sw t2, EBU_BUSCON1(t1)
1073:
108 j ra
109 nop
110
111 .end ebu_init
112
113
114/*
115 * void cgu_init(long)
116 *
117 * a0 has the clock value
118 */
119 .globl cgu_init
120 .ent cgu_init
121cgu_init:
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100122__cgu_init:
wdenk7cb22f92003-12-27 19:24:54 +0000123
124 li t1, CGU_MODUL_BASE
125
126 li t3, 100000000
127 beq a0, t3, 1f
128 nop
129 li t3, 133000000
130 beq a0, t3, 2f
131 nop
132 li t3, 150000000
133 beq a0, t3, 3f
134 nop
135 b 5f
136 nop
137
138 /* 100 MHz clock */
1391:
140 li t2, 0x80000014
141 sw t2, CGU_DIVCR(t1)
142 li t2, 0x80000000
143 sw t2, CGU_MUXCR(t1)
144 li t2, 0x800B0001
145 b 5f
146 sw t2, CGU_PLL1CR(t1) /* delay slot */
147
148 /* 133 MHz clock */
1492:
150 li t2, 0x80000054
151 sw t2, CGU_DIVCR(t1)
152 li t2, 0x80000000
153 sw t2, CGU_MUXCR(t1)
154 li t2, 0x800B0001
155 b 5f
156 sw t2, CGU_PLL1CR(t1) /* delay slot */
157
158 /* 150 MHz clock */
1593:
160 li t2, 0x80000017
161 sw t2, CGU_DIVCR(t1)
162 li t2, 0xC00B0001
163 sw t2, CGU_PLL1CR(t1)
164 li t3, 0x80000000
1654:
166 lw t2, CGU_PLL1SR(t1)
167 and t2, t2, t3
168 beq t2, zero, 4b
169 nop
170 li t2, 0x80000001
171 sw t2, CGU_MUXCR(t1)
1725:
173 j ra
174 nop
175
176 .end cgu_init
177
178
wdenk68766092004-01-29 09:22:58 +0000179/*
180 * void sdram_init(long)
181 *
182 * a0 has the clock value
183 */
184 .globl sdram_init
185 .ent sdram_init
186sdram_init:
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100187__sdram_init:
wdenk68766092004-01-29 09:22:58 +0000188
189 li t1, MC_MODUL_BASE
190
wdenkcf56e112004-02-20 22:02:48 +0000191#if 0
wdenk68766092004-01-29 09:22:58 +0000192 /* Disable memory controller before changing any of its registers */
193 sw zero, MC_CTRLENA(t1)
wdenkcf56e112004-02-20 22:02:48 +0000194#endif
wdenk68766092004-01-29 09:22:58 +0000195
196 li t2, 100000000
197 beq a0, t2, 1f
198 nop
199 li t2, 133000000
200 beq a0, t2, 2f
201 nop
202 li t2, 150000000
203 beq a0, t2, 3f
204 nop
205 b 5f
206 nop
207
208 /* 100 MHz clock */
2091:
210 /* Set clock ratio (clkrat=1:1, rddel=3) */
211 li t2, 0x00000003
212 sw t2, MC_IOGP(t1)
213
214 /* Set sdram refresh rate (4K/64ms @ 100MHz) */
215 li t2, 0x0000061A
216 b 4f
217 sw t2, MC_TREFRESH(t1)
218
219 /* 133 MHz clock */
2202:
221 /* Set clock ratio (clkrat=1:1, rddel=3) */
222 li t2, 0x00000003
223 sw t2, MC_IOGP(t1)
224
225 /* Set sdram refresh rate (4K/64ms @ 133MHz) */
226 li t2, 0x00000822
227 b 4f
228 sw t2, MC_TREFRESH(t1)
229
230 /* 150 MHz clock */
2313:
232 /* Set clock ratio (clkrat=3:2, rddel=4) */
233 li t2, 0x00000014
234 sw t2, MC_IOGP(t1)
235
236 /* Set sdram refresh rate (4K/64ms @ 150MHz) */
237 li t2, 0x00000927
238 sw t2, MC_TREFRESH(t1)
239
2404:
241 /* Clear Error log registers */
242 sw zero, MC_ERRCAUSE(t1)
243 sw zero, MC_ERRADDR(t1)
244
245 /* Clear Power-down registers */
246 sw zero, MC_SELFRFSH(t1)
247
248 /* Set CAS Latency */
249 li t2, 0x00000020 /* CL = 2 */
250 sw t2, MC_MRSCODE(t1)
251
252 /* Set word width to 16 bit */
253 li t2, 0x2
254 sw t2, MC_CFGDW(t1)
255
256 /* Set CS0 to SDRAM parameters */
257 li t2, 0x000014C9
258 sw t2, MC_CFGPB0(t1)
259
260 /* Set SDRAM latency parameters */
261 li t2, 0x00026325 /* BC PC100 */
262 sw t2, MC_LATENCY(t1)
263
2645:
265 /* Finally enable the controller */
266 li t2, 0x00000001
267 sw t2, MC_CTRLENA(t1)
268
269 j ra
270 nop
271
272 .end sdram_init
273
274
wdenk400558b2005-04-02 23:52:25 +0000275 .globl lowlevel_init
276 .ent lowlevel_init
277lowlevel_init:
wdenkc0218802003-03-27 12:09:35 +0000278
Shinya Kuribayashi26138622008-03-25 21:30:07 +0900279 /* Disable Watchdog.
280 */
281 la t9, disable_incaip_wdt
282 jalr t9
283 nop
284
wdenk68766092004-01-29 09:22:58 +0000285 /* EBU, CGU and SDRAM Initialization.
wdenkc0218802003-03-27 12:09:35 +0000286 */
wdenk7cb22f92003-12-27 19:24:54 +0000287 li a0, CPU_CLOCK_RATE
288 move t0, ra
wdenkc0218802003-03-27 12:09:35 +0000289
wdenk68766092004-01-29 09:22:58 +0000290 /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
wdenk7cb22f92003-12-27 19:24:54 +0000291 * modify t0 and a0.
wdenkc0218802003-03-27 12:09:35 +0000292 */
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100293 bal __cgu_init
wdenk68766092004-01-29 09:22:58 +0000294 nop
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100295 bal __ebu_init
wdenk7cb22f92003-12-27 19:24:54 +0000296 nop
Wolfgang Denkf013dac2005-12-04 00:40:34 +0100297 bal __sdram_init
wdenk7cb22f92003-12-27 19:24:54 +0000298 nop
299 move ra, t0
wdenkc0218802003-03-27 12:09:35 +0000300
wdenkc0218802003-03-27 12:09:35 +0000301 j ra
302 nop
wdenk68766092004-01-29 09:22:58 +0000303
wdenk400558b2005-04-02 23:52:25 +0000304 .end lowlevel_init