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wdenkc0218802003-03-27 12:09:35 +00001/*
2 * Memory sub-system initialization code for INCA-IP development board.
3 *
4 * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkd4ca31c2004-01-02 14:00:00 +000016 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenkc0218802003-03-27 12:09:35 +000017 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/regdef.h>
28
29
wdenkd4ca31c2004-01-02 14:00:00 +000030#define EBU_MODUL_BASE 0xB8000200
31#define EBU_CLC(value) 0x0000(value)
32#define EBU_CON(value) 0x0010(value)
33#define EBU_ADDSEL0(value) 0x0020(value)
34#define EBU_ADDSEL1(value) 0x0024(value)
35#define EBU_ADDSEL2(value) 0x0028(value)
36#define EBU_BUSCON0(value) 0x0060(value)
37#define EBU_BUSCON1(value) 0x0064(value)
38#define EBU_BUSCON2(value) 0x0068(value)
wdenkc0218802003-03-27 12:09:35 +000039
wdenkd4ca31c2004-01-02 14:00:00 +000040#define MC_MODUL_BASE 0xBF800000
41#define MC_ERRCAUSE(value) 0x0100(value)
42#define MC_ERRADDR(value) 0x0108(value)
43#define MC_IOGP(value) 0x0800(value)
44#define MC_SELFRFSH(value) 0x0A00(value)
45#define MC_CTRLENA(value) 0x1000(value)
46#define MC_MRSCODE(value) 0x1008(value)
47#define MC_CFGDW(value) 0x1010(value)
48#define MC_CFGPB0(value) 0x1018(value)
49#define MC_LATENCY(value) 0x1038(value)
50#define MC_TREFRESH(value) 0x1040(value)
wdenkc0218802003-03-27 12:09:35 +000051
wdenkd4ca31c2004-01-02 14:00:00 +000052#define CGU_MODUL_BASE 0xBF107000
53#define CGU_PLL1CR(value) 0x0008(value)
54#define CGU_DIVCR(value) 0x0010(value)
55#define CGU_MUXCR(value) 0x0014(value)
56#define CGU_PLL1SR(value) 0x000C(value)
wdenkc0218802003-03-27 12:09:35 +000057
wdenkd4ca31c2004-01-02 14:00:00 +000058 .set noreorder
wdenk7cb22f92003-12-27 19:24:54 +000059
60
61/*
62 * void ebu_init(long)
63 *
64 * a0 has the clock value we are going to run at
65 */
66 .globl ebu_init
67 .ent ebu_init
68ebu_init:
69
70 li t1, EBU_MODUL_BASE
71 li t2, 0xA0000041
72 sw t2, EBU_ADDSEL0(t1)
73 li t2, 0xA0800041
74 sw t2, EBU_ADDSEL2(t1)
75 li t2, 0xBE0000F1
76 sw t2, EBU_ADDSEL1(t1)
77
78 li t3, 100000000
79 beq a0, t3, 1f
80 nop
81 li t3, 133000000
82 beq a0, t3, 2f
83 nop
84 li t3, 150000000
85 beq a0, t3, 2f
86 nop
87 b 3f
88 nop
89
90 /* 100 MHz */
911:
92 li t2, 0x8841417D
93 sw t2, EBU_BUSCON0(t1)
94 sw t2, EBU_BUSCON2(t1)
95 li t2, 0x684142BD
96 b 3f
97 sw t2, EBU_BUSCON1(t1) /* delay slot */
98
99 /* 133 or 150 MHz */
1002:
101 li t2, 0x8841417E
102 sw t2, EBU_BUSCON0(t1)
103 sw t2, EBU_BUSCON2(t1)
104 li t2, 0x684143FD
105 sw t2, EBU_BUSCON1(t1)
1063:
107 j ra
108 nop
109
110 .end ebu_init
111
112
113/*
114 * void cgu_init(long)
115 *
116 * a0 has the clock value
117 */
118 .globl cgu_init
119 .ent cgu_init
120cgu_init:
121
122 li t1, CGU_MODUL_BASE
123
124 li t3, 100000000
125 beq a0, t3, 1f
126 nop
127 li t3, 133000000
128 beq a0, t3, 2f
129 nop
130 li t3, 150000000
131 beq a0, t3, 3f
132 nop
133 b 5f
134 nop
135
136 /* 100 MHz clock */
1371:
138 li t2, 0x80000014
139 sw t2, CGU_DIVCR(t1)
140 li t2, 0x80000000
141 sw t2, CGU_MUXCR(t1)
142 li t2, 0x800B0001
143 b 5f
144 sw t2, CGU_PLL1CR(t1) /* delay slot */
145
146 /* 133 MHz clock */
1472:
148 li t2, 0x80000054
149 sw t2, CGU_DIVCR(t1)
150 li t2, 0x80000000
151 sw t2, CGU_MUXCR(t1)
152 li t2, 0x800B0001
153 b 5f
154 sw t2, CGU_PLL1CR(t1) /* delay slot */
155
156 /* 150 MHz clock */
1573:
158 li t2, 0x80000017
159 sw t2, CGU_DIVCR(t1)
160 li t2, 0xC00B0001
161 sw t2, CGU_PLL1CR(t1)
162 li t3, 0x80000000
1634:
164 lw t2, CGU_PLL1SR(t1)
165 and t2, t2, t3
166 beq t2, zero, 4b
167 nop
168 li t2, 0x80000001
169 sw t2, CGU_MUXCR(t1)
1705:
171 j ra
172 nop
173
174 .end cgu_init
175
176
wdenk68766092004-01-29 09:22:58 +0000177/*
178 * void sdram_init(long)
179 *
180 * a0 has the clock value
181 */
182 .globl sdram_init
183 .ent sdram_init
184sdram_init:
185
186 li t1, MC_MODUL_BASE
187
wdenkcf56e112004-02-20 22:02:48 +0000188#if 0
wdenk68766092004-01-29 09:22:58 +0000189 /* Disable memory controller before changing any of its registers */
190 sw zero, MC_CTRLENA(t1)
wdenkcf56e112004-02-20 22:02:48 +0000191#endif
wdenk68766092004-01-29 09:22:58 +0000192
193 li t2, 100000000
194 beq a0, t2, 1f
195 nop
196 li t2, 133000000
197 beq a0, t2, 2f
198 nop
199 li t2, 150000000
200 beq a0, t2, 3f
201 nop
202 b 5f
203 nop
204
205 /* 100 MHz clock */
2061:
207 /* Set clock ratio (clkrat=1:1, rddel=3) */
208 li t2, 0x00000003
209 sw t2, MC_IOGP(t1)
210
211 /* Set sdram refresh rate (4K/64ms @ 100MHz) */
212 li t2, 0x0000061A
213 b 4f
214 sw t2, MC_TREFRESH(t1)
215
216 /* 133 MHz clock */
2172:
218 /* Set clock ratio (clkrat=1:1, rddel=3) */
219 li t2, 0x00000003
220 sw t2, MC_IOGP(t1)
221
222 /* Set sdram refresh rate (4K/64ms @ 133MHz) */
223 li t2, 0x00000822
224 b 4f
225 sw t2, MC_TREFRESH(t1)
226
227 /* 150 MHz clock */
2283:
229 /* Set clock ratio (clkrat=3:2, rddel=4) */
230 li t2, 0x00000014
231 sw t2, MC_IOGP(t1)
232
233 /* Set sdram refresh rate (4K/64ms @ 150MHz) */
234 li t2, 0x00000927
235 sw t2, MC_TREFRESH(t1)
236
2374:
238 /* Clear Error log registers */
239 sw zero, MC_ERRCAUSE(t1)
240 sw zero, MC_ERRADDR(t1)
241
242 /* Clear Power-down registers */
243 sw zero, MC_SELFRFSH(t1)
244
245 /* Set CAS Latency */
246 li t2, 0x00000020 /* CL = 2 */
247 sw t2, MC_MRSCODE(t1)
248
249 /* Set word width to 16 bit */
250 li t2, 0x2
251 sw t2, MC_CFGDW(t1)
252
253 /* Set CS0 to SDRAM parameters */
254 li t2, 0x000014C9
255 sw t2, MC_CFGPB0(t1)
256
257 /* Set SDRAM latency parameters */
258 li t2, 0x00026325 /* BC PC100 */
259 sw t2, MC_LATENCY(t1)
260
2615:
262 /* Finally enable the controller */
263 li t2, 0x00000001
264 sw t2, MC_CTRLENA(t1)
265
266 j ra
267 nop
268
269 .end sdram_init
270
271
wdenkc0218802003-03-27 12:09:35 +0000272 .globl memsetup
wdenk7cb22f92003-12-27 19:24:54 +0000273 .ent memsetup
wdenkc0218802003-03-27 12:09:35 +0000274memsetup:
275
wdenk68766092004-01-29 09:22:58 +0000276 /* EBU, CGU and SDRAM Initialization.
wdenkc0218802003-03-27 12:09:35 +0000277 */
wdenk7cb22f92003-12-27 19:24:54 +0000278 li a0, CPU_CLOCK_RATE
279 move t0, ra
wdenkc0218802003-03-27 12:09:35 +0000280
wdenk68766092004-01-29 09:22:58 +0000281 /* We rely on the fact that neither ebu_init() nor cgu_init() nor sdram_init()
wdenk7cb22f92003-12-27 19:24:54 +0000282 * modify t0 and a0.
wdenkc0218802003-03-27 12:09:35 +0000283 */
wdenk68766092004-01-29 09:22:58 +0000284 bal cgu_init
285 nop
wdenk7cb22f92003-12-27 19:24:54 +0000286 bal ebu_init
287 nop
wdenk68766092004-01-29 09:22:58 +0000288 bal sdram_init
wdenk7cb22f92003-12-27 19:24:54 +0000289 nop
290 move ra, t0
wdenkc0218802003-03-27 12:09:35 +0000291
wdenkc0218802003-03-27 12:09:35 +0000292 j ra
293 nop
wdenk68766092004-01-29 09:22:58 +0000294
wdenk7cb22f92003-12-27 19:24:54 +0000295 .end memsetup