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Paul Gortmaker91e25762007-01-16 11:38:14 -05001/*
2 * sbc8349.c -- WindRiver SBC8349 board support.
3 * Copyright (c) 2006-2007 Wind River Systems, Inc.
4 *
5 * Paul Gortmaker <paul.gortmaker@windriver.com>
6 * Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Paul Gortmaker91e25762007-01-16 11:38:14 -05009 */
10
11#include <common.h>
12#include <ioports.h>
13#include <mpc83xx.h>
14#include <asm/mpc8349_pci.h>
15#include <i2c.h>
Paul Gortmaker91e25762007-01-16 11:38:14 -050016#include <spd_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060017#include <miiphy.h>
Kim Phillipsb3458d22007-12-20 15:57:28 -060018#if defined(CONFIG_OF_LIBFDT)
Paul Gortmaker2408b3f2007-12-20 12:58:16 -050019#include <libfdt.h>
Paul Gortmaker91e25762007-01-16 11:38:14 -050020#endif
21
22int fixed_sdram(void);
23void sdram_init(void);
24
Peter Tyser0f898602009-05-22 17:23:24 -050025#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
Paul Gortmaker91e25762007-01-16 11:38:14 -050026void ddr_enable_ecc(unsigned int dram_size);
27#endif
28
29#ifdef CONFIG_BOARD_EARLY_INIT_F
30int board_early_init_f (void)
31{
32 return 0;
33}
34#endif
35
36#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
37
Becky Bruce9973e3c2008-06-09 16:03:40 -050038phys_size_t initdram (int board_type)
Paul Gortmaker91e25762007-01-16 11:38:14 -050039{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020040 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Paul Gortmaker91e25762007-01-16 11:38:14 -050041 u32 msize = 0;
42
43 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
44 return -1;
45
Paul Gortmaker91e25762007-01-16 11:38:14 -050046 /* DDR SDRAM - Main SODIMM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
Paul Gortmaker91e25762007-01-16 11:38:14 -050048#if defined(CONFIG_SPD_EEPROM)
49 msize = spd_sdram();
50#else
51 msize = fixed_sdram();
52#endif
53 /*
54 * Initialize SDRAM if it is on local bus.
55 */
56 sdram_init();
57
58#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
59 /*
60 * Initialize and enable DDR ECC.
61 */
62 ddr_enable_ecc(msize * 1024 * 1024);
63#endif
Paul Gortmaker91e25762007-01-16 11:38:14 -050064 /* return total bus SDRAM size(bytes) -- DDR */
65 return (msize * 1024 * 1024);
66}
67
68#if !defined(CONFIG_SPD_EEPROM)
69/*************************************************************************
70 * fixed sdram init -- doesn't use serial presence detect.
71 ************************************************************************/
72int fixed_sdram(void)
73{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Joe Hershberger2e651b22011-10-11 23:57:31 -050075 u32 msize = CONFIG_SYS_DDR_SIZE;
76 u32 ddr_size = msize << 20; /* DDR size in bytes */
77 u32 ddr_size_log2 = __ilog2(msize);
Paul Gortmaker91e25762007-01-16 11:38:14 -050078
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Paul Gortmaker91e25762007-01-16 11:38:14 -050080 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#if (CONFIG_SYS_DDR_SIZE != 256)
Paul Gortmaker91e25762007-01-16 11:38:14 -050083#warning Currently any ddr size other than 256 is not supported
84#endif
Joe Hershberger2e651b22011-10-11 23:57:31 -050085
86#if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
87#warning Chip select bounds is only configurable in 16MB increments
88#endif
89 im->ddr.csbnds[2].csbnds =
90 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
91 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
92 CSBNDS_EA_SHIFT) & CSBNDS_EA);
93 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
Paul Gortmaker91e25762007-01-16 11:38:14 -050094
95 /* currently we use only one CS, so disable the other banks */
96 im->ddr.cs_config[0] = 0;
97 im->ddr.cs_config[1] = 0;
98 im->ddr.cs_config[3] = 0;
99
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
101 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500102
103 im->ddr.sdram_cfg =
104 SDRAM_CFG_SREN
105#if defined(CONFIG_DDR_2T_TIMING)
106 | SDRAM_CFG_2T_EN
107#endif
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500108 | SDRAM_CFG_SDRAM_TYPE_DDR1;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500109#if defined (CONFIG_DDR_32BIT)
110 /* for 32-bit mode burst length is 8 */
111 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
112#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500116 udelay(200);
117
118 /* enable DDR controller */
119 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
120 return msize;
121}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#endif/*!CONFIG_SYS_SPD_EEPROM*/
Paul Gortmaker91e25762007-01-16 11:38:14 -0500123
124
125int checkboard (void)
126{
127 puts("Board: Wind River SBC834x\n");
128 return 0;
129}
130
131/*
132 * if board is fitted with SDRAM
133 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#if defined(CONFIG_SYS_BR2_PRELIM) \
135 && defined(CONFIG_SYS_OR2_PRELIM) \
136 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
137 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500138/*
139 * Initialize SDRAM memory on the Local Bus.
140 */
141
142void sdram_init(void)
143{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Becky Brucef51cdaf2010-06-17 11:37:20 -0500145 volatile fsl_lbc_t *lbc = &immap->im_lbc;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500147
148 puts("\n SDRAM on Local Bus: ");
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149 print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
Paul Gortmaker91e25762007-01-16 11:38:14 -0500150
151 /*
152 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
153 */
154
155 /* setup mtrpt, lsrt and lbcr for LB bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
157 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
158 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500159 asm("sync");
160
161 /*
162 * Configure the SDRAM controller Machine Mode Register.
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500165
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500167 asm("sync");
168 *sdram_addr = 0xff;
169 udelay(100);
170
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500172 asm("sync");
173 /*1 times*/
174 *sdram_addr = 0xff;
175 udelay(100);
176 /*2 times*/
177 *sdram_addr = 0xff;
178 udelay(100);
179 /*3 times*/
180 *sdram_addr = 0xff;
181 udelay(100);
182 /*4 times*/
183 *sdram_addr = 0xff;
184 udelay(100);
185 /*5 times*/
186 *sdram_addr = 0xff;
187 udelay(100);
188 /*6 times*/
189 *sdram_addr = 0xff;
190 udelay(100);
191 /*7 times*/
192 *sdram_addr = 0xff;
193 udelay(100);
194 /*8 times*/
195 *sdram_addr = 0xff;
196 udelay(100);
197
198 /* 0x58636733; mode register write operation */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500200 asm("sync");
201 *sdram_addr = 0xff;
202 udelay(100);
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Paul Gortmaker91e25762007-01-16 11:38:14 -0500205 asm("sync");
206 *sdram_addr = 0xff;
207 udelay(100);
208}
209#else
210void sdram_init(void)
211{
212 puts(" SDRAM on Local Bus: Disabled in config\n");
213}
214#endif
215
Paul Gortmaker2408b3f2007-12-20 12:58:16 -0500216#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600217int ft_board_setup(void *blob, bd_t *bd)
Paul Gortmaker91e25762007-01-16 11:38:14 -0500218{
Paul Gortmaker2408b3f2007-12-20 12:58:16 -0500219 ft_cpu_setup(blob, bd);
220#ifdef CONFIG_PCI
221 ft_pci_setup(blob, bd);
222#endif
Simon Glasse895a4b2014-10-23 18:58:47 -0600223
224 return 0;
Paul Gortmaker91e25762007-01-16 11:38:14 -0500225}
226#endif