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wdenk324f6cf2002-10-07 21:13:39 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
wdenk228f29a2002-12-08 09:53:23 +000022 *
23 * Be sure to mark tests to be run before relocation as such with the
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024 * CONFIG_SYS_POST_PREREL flag so that logging is done correctly if the
wdenk228f29a2002-12-08 09:53:23 +000025 * logbuffer support is enabled.
wdenk324f6cf2002-10-07 21:13:39 +000026 */
27
28#include <common.h>
29
wdenk324f6cf2002-10-07 21:13:39 +000030#include <post.h>
31
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020032extern int ocm_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000033extern int cache_post_test (int flags);
34extern int watchdog_post_test (int flags);
35extern int i2c_post_test (int flags);
36extern int rtc_post_test (int flags);
37extern int memory_post_test (int flags);
38extern int cpu_post_test (int flags);
Igor Lisitsina11e0692007-03-28 19:06:19 +040039extern int fpu_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000040extern int uart_post_test (int flags);
41extern int ether_post_test (int flags);
42extern int spi_post_test (int flags);
43extern int usb_post_test (int flags);
44extern int spr_post_test (int flags);
wdenk4532cb62003-04-27 22:52:51 +000045extern int sysmon_post_test (int flags);
wdenk5a8c51c2004-04-15 21:16:42 +000046extern int dsp_post_test (int flags);
wdenk79fa88f2004-06-07 23:46:25 +000047extern int codec_post_test (int flags);
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +020048extern int ecc_post_test (int flags);
Mike Frysingerf6f73952011-05-10 13:35:40 +000049extern int flash_post_test(int flags);
wdenk4532cb62003-04-27 22:52:51 +000050
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010051extern int dspic_init_post_test (int flags);
52extern int dspic_post_test (int flags);
53extern int gdc_post_test (int flags);
54extern int fpga_post_test (int flags);
55extern int lwmon5_watchdog_post_test(int flags);
56extern int sysmon1_post_test(int flags);
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +020057extern int coprocessor_post_test(int flags);
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010058
wdenk4532cb62003-04-27 22:52:51 +000059extern int sysmon_init_f (void);
60
61extern void sysmon_reloc (void);
62
wdenk324f6cf2002-10-07 21:13:39 +000063
64struct post_test post_list[] =
65{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#if CONFIG_POST & CONFIG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020067 {
68 "OCM test",
69 "ocm",
70 "This test checks on chip memory (OCM).",
Yuri Tikhonov7845d492008-05-08 15:46:02 +020071 POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020072 &ocm_post_test,
73 NULL,
74 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075 CONFIG_SYS_POST_OCM
Yuri Tikhonov6e8ec682008-05-08 15:42:47 +020076 },
77#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020078#if CONFIG_POST & CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000079 {
wdenk8bde7f72003-06-27 21:31:46 +000080 "Cache test",
81 "cache",
82 "This test verifies the CPU cache operation.",
83 POST_RAM | POST_ALWAYS,
84 &cache_post_test,
85 NULL,
86 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087 CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000088 },
89#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +010091#if defined(CONFIG_POST_WATCHDOG)
92 CONFIG_POST_WATCHDOG,
93#else
wdenk324f6cf2002-10-07 21:13:39 +000094 {
wdenk8bde7f72003-06-27 21:31:46 +000095 "Watchdog timer test",
96 "watchdog",
97 "This test checks the watchdog timer.",
wdenk8564acf2003-07-14 22:13:32 +000098 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
wdenk8bde7f72003-06-27 21:31:46 +000099 &watchdog_post_test,
100 NULL,
101 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102 CONFIG_SYS_POST_WATCHDOG
wdenk324f6cf2002-10-07 21:13:39 +0000103 },
104#endif
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100105#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#if CONFIG_POST & CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +0000107 {
wdenk8bde7f72003-06-27 21:31:46 +0000108 "I2C test",
109 "i2c",
110 "This test verifies the I2C operation.",
111 POST_RAM | POST_ALWAYS,
112 &i2c_post_test,
113 NULL,
114 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +0000116 },
117#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#if CONFIG_POST & CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000119 {
wdenk8bde7f72003-06-27 21:31:46 +0000120 "RTC test",
121 "rtc",
122 "This test verifies the RTC operation.",
wdenk8564acf2003-07-14 22:13:32 +0000123 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000124 &rtc_post_test,
125 NULL,
126 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000128 },
129#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000131 {
wdenk8bde7f72003-06-27 21:31:46 +0000132 "Memory test",
133 "memory",
134 "This test checks RAM.",
wdenk8564acf2003-07-14 22:13:32 +0000135 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
wdenk8bde7f72003-06-27 21:31:46 +0000136 &memory_post_test,
137 NULL,
138 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139 CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000140 },
141#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#if CONFIG_POST & CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000143 {
wdenk8bde7f72003-06-27 21:31:46 +0000144 "CPU test",
145 "cpu",
146 "This test verifies the arithmetic logic unit of"
147 " CPU.",
148 POST_RAM | POST_ALWAYS,
149 &cpu_post_test,
150 NULL,
151 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152 CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000153 },
154#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#if CONFIG_POST & CONFIG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400156 {
157 "FPU test",
158 "fpu",
159 "This test verifies the arithmetic logic unit of"
160 " FPU.",
161 POST_RAM | POST_ALWAYS,
162 &fpu_post_test,
163 NULL,
164 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165 CONFIG_SYS_POST_FPU
Igor Lisitsina11e0692007-03-28 19:06:19 +0400166 },
167#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#if CONFIG_POST & CONFIG_SYS_POST_UART
Stefan Roese834a45d2010-10-07 14:16:25 +0200169#if defined(CONFIG_POST_UART)
170 CONFIG_POST_UART,
171#else
wdenk324f6cf2002-10-07 21:13:39 +0000172 {
wdenk8bde7f72003-06-27 21:31:46 +0000173 "UART test",
174 "uart",
175 "This test verifies the UART operation.",
wdenk8564acf2003-07-14 22:13:32 +0000176 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk8bde7f72003-06-27 21:31:46 +0000177 &uart_post_test,
178 NULL,
179 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 CONFIG_SYS_POST_UART
wdenk324f6cf2002-10-07 21:13:39 +0000181 },
Stefan Roese834a45d2010-10-07 14:16:25 +0200182#endif /* CONFIG_POST_UART */
wdenk324f6cf2002-10-07 21:13:39 +0000183#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#if CONFIG_POST & CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000185 {
wdenk8bde7f72003-06-27 21:31:46 +0000186 "ETHERNET test",
187 "ethernet",
188 "This test verifies the ETHERNET operation.",
189 POST_RAM | POST_ALWAYS | POST_MANUAL,
190 &ether_post_test,
191 NULL,
192 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000194 },
195#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#if CONFIG_POST & CONFIG_SYS_POST_SPI
wdenk324f6cf2002-10-07 21:13:39 +0000197 {
wdenk8bde7f72003-06-27 21:31:46 +0000198 "SPI test",
199 "spi",
200 "This test verifies the SPI operation.",
201 POST_RAM | POST_ALWAYS | POST_MANUAL,
202 &spi_post_test,
203 NULL,
204 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205 CONFIG_SYS_POST_SPI
wdenk324f6cf2002-10-07 21:13:39 +0000206 },
207#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#if CONFIG_POST & CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000209 {
wdenk8bde7f72003-06-27 21:31:46 +0000210 "USB test",
211 "usb",
212 "This test verifies the USB operation.",
213 POST_RAM | POST_ALWAYS | POST_MANUAL,
214 &usb_post_test,
215 NULL,
216 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217 CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000218 },
219#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#if CONFIG_POST & CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000221 {
wdenk8bde7f72003-06-27 21:31:46 +0000222 "SPR test",
223 "spr",
224 "This test checks SPR contents.",
Stefan Roeseb2e21422008-01-09 10:38:58 +0100225 POST_RAM | POST_ALWAYS,
wdenk8bde7f72003-06-27 21:31:46 +0000226 &spr_post_test,
227 NULL,
228 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229 CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000230 },
231#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#if CONFIG_POST & CONFIG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000233 {
wdenk8bde7f72003-06-27 21:31:46 +0000234 "SYSMON test",
235 "sysmon",
236 "This test monitors system hardware.",
237 POST_RAM | POST_ALWAYS,
238 &sysmon_post_test,
239 &sysmon_init_f,
240 &sysmon_reloc,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241 CONFIG_SYS_POST_SYSMON
wdenk4532cb62003-04-27 22:52:51 +0000242 },
243#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#if CONFIG_POST & CONFIG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000245 {
246 "DSP test",
247 "dsp",
248 "This test checks any connected DSP(s).",
Sascha Laue5744ddc2008-05-30 09:48:14 +0200249 POST_RAM | POST_ALWAYS | POST_MANUAL,
wdenk5a8c51c2004-04-15 21:16:42 +0000250 &dsp_post_test,
251 NULL,
252 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253 CONFIG_SYS_POST_DSP
wdenk5a8c51c2004-04-15 21:16:42 +0000254 },
255#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#if CONFIG_POST & CONFIG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000257 {
258 "CODEC test",
259 "codec",
260 "This test checks any connected codec(s).",
261 POST_RAM | POST_MANUAL,
262 &codec_post_test,
263 NULL,
264 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265 CONFIG_SYS_POST_CODEC
wdenk79fa88f2004-06-07 23:46:25 +0000266 },
267#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#if CONFIG_POST & CONFIG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200269 {
270 "ECC test",
271 "ecc",
Larry Johnson8dafa872008-01-12 23:35:33 -0500272 "This test checks the ECC facility of memory.",
273 POST_ROM | POST_ALWAYS | POST_PREREL,
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200274 &ecc_post_test,
275 NULL,
276 NULL,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277 CONFIG_SYS_POST_ECC
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200278 },
279#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100281 CONFIG_POST_BSPEC1,
282#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100284 CONFIG_POST_BSPEC2,
285#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200286#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100287 CONFIG_POST_BSPEC3,
288#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100290 CONFIG_POST_BSPEC4,
291#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5
Yuri Tikhonov65b20dc2008-02-04 14:10:42 +0100293 CONFIG_POST_BSPEC5,
294#endif
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200295#if CONFIG_POST & CONFIG_SYS_POST_COPROC
296 {
297 "Coprocessors communication test",
298 "coproc_com",
299 "This test checks communication with coprocessors.",
300 POST_RAM | POST_ALWAYS | POST_CRITICAL,
301 &coprocessor_post_test,
302 NULL,
303 NULL,
304 CONFIG_SYS_POST_COPROC
Mike Frysingerf6f73952011-05-10 13:35:40 +0000305 },
306#endif
307#if CONFIG_POST & CONFIG_SYS_POST_FLASH
308 {
309 "Parallel NOR flash test",
310 "flash",
311 "This test verifies parallel flash operations.",
312 POST_RAM | POST_SLOWTEST | POST_MANUAL,
313 &flash_post_test,
314 NULL,
315 NULL,
316 CONFIG_SYS_POST_FLASH
317 },
Anatolij Gustschin29fd7ce2010-04-24 19:27:11 +0200318#endif
wdenk324f6cf2002-10-07 21:13:39 +0000319};
320
Mike Frysingerd2397812011-05-10 07:28:35 +0000321unsigned int post_list_size = ARRAY_SIZE(post_list);