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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 4411b2aea7aa06d7b4aa5f4a7b36957af9b95e08 / . / arch / arm / cpu / tegra30-common / pinmux.c
blob: eecf0580bc9011d74843c0f6cd5f83187c8cdc22 [file] [log] [blame]
Tom Warrenb2871032012-12-11 13:34:15 +0000[diff] [blame]1/*
Tom Warren8ca79b22013-03-06 16:16:22 -0700[diff] [blame]2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
Tom Warrenb2871032012-12-11 13:34:15 +0000[diff] [blame]3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra30 pin multiplexing functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/tegra.h>
22#include <asm/arch/pinmux.h>
23
24struct tegra_pingroup_desc {
25 const char *name;
26 enum pmux_func funcs[4];
27 enum pmux_func func_safe;
28 enum pmux_vddio vddio;
29 enum pmux_pin_io io;
30};
31
32#define PMUX_MUXCTL_SHIFT 0
33#define PMUX_PULL_SHIFT 2
34#define PMUX_TRISTATE_SHIFT 4
35#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
36#define PMUX_IO_SHIFT 5
37#define PMUX_OD_SHIFT 6
38#define PMUX_LOCK_SHIFT 7
39#define PMUX_IO_RESET_SHIFT 8
40
Tom Warren8ca79b22013-03-06 16:16:22 -0700[diff] [blame]41#define PGRP_HSM_SHIFT 2
42#define PGRP_SCHMT_SHIFT 3
43#define PGRP_LPMD_SHIFT 4
44#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
45#define PGRP_DRVDN_SHIFT 12
46#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
47#define PGRP_DRVUP_SHIFT 20
48#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
49#define PGRP_SLWR_SHIFT 28
50#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
51#define PGRP_SLWF_SHIFT 30
52#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
53
Tom Warrenb2871032012-12-11 13:34:15 +0000[diff] [blame]54/* Convenient macro for defining pin group properties */
55#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
56 { \
57 .vddio = PMUX_VDDIO_ ## vdd, \
58 .funcs = { \
59 PMUX_FUNC_ ## f0, \
60 PMUX_FUNC_ ## f1, \
61 PMUX_FUNC_ ## f2, \
62 PMUX_FUNC_ ## f3, \
63 }, \
64 .func_safe = PMUX_FUNC_RSVD1, \
65 .io = PMUX_PIN_ ## iod, \
66 }
67
68/* Input and output pins */
69#define PINI(pg_name, vdd, f0, f1, f2, f3) \
70 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
71#define PINO(pg_name, vdd, f0, f1, f2, f3) \
72 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
73
74const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
75 /* NAME VDD f0 f1 f2 f3 */
76 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
77 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
78 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
79 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
80 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
81 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
82 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
83 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
84 PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
85 PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
86 PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
87 PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
88 PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
89 PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
90 PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
91 PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
92 PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
93 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
94 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
95 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
96 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
97 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
98 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
99 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
100 PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
101 PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
102 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
103 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
104 PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
105 PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
106 PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
107 PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
108 PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
109 PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
110 PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
111 PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
112 PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
113 PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
114 PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
115 PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
116 PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
117 PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
118 PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
119 PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
120 PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
121 PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
122 PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
123 PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
124 PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
125 PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
126 PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
127 PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
128 PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
129 PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
130 PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
131 PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
132 PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
133 PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
134 PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
135 PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
136 PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
137 PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
138 PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
139 PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
140 PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
141 PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
142 PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
143 PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
144 PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
145 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
146 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
147 PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
148 PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
149 PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
150 PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
151 PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
152 PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
153 PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
154 PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
155 PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
156 PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
157 PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
158 PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
159 PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
160 PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
161 PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
162 PINI(VI_MCLK, VI, VI, VI, VI, VI),
163 PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
164 PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
165 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
166 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
167 PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
168 PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
169 PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
170 PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
171 PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
172 PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
173 PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
174 PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
175 PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
176 PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
177 PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
178 PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
179 PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
180 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
181 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
182 PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
183 PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
184 PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
185 PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
186 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
187 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
188 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
189 PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
190 PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
191 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
192 PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
193 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
194 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
195 PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
196 PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
197 PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
198 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
199 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
200 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
201 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
202 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
203 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
204 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
205 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
206 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
207 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
208 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
209 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
210 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
211 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
212 PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
213 PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
214 PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
215 PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
216 PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
217 PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
218 PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
219 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
220 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
221 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
222 PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
223 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
224 PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
225 PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
226 PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
227 PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
228 PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
229 PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
230 PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
231 PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
232 PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
233 PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
234 PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
235 PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
236 PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
237 PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
238 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
239 PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
240 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
241 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
242 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
243 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
244 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
245 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
246 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
247 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
248 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
249 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
250 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
251 PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
252 PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
253 PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
254 PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
255 PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
256 PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
257 PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
258 PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
259 PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
260 PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
261 PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
262 PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
263 PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
264 PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
265 PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
266 PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
267 PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
268 PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
269 PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
270 PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
271 PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
272 PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
273 PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
274 PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
275 PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
276 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
277 PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
278 PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
279 PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
280 PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
281 PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
282 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
283 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
284 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
285 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
286 PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
287 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
288 PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
289 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
290 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
291 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
292 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
293 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
294 PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
295 PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
296 PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
297 PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
298 PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
299 PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
300 PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
301 PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
302 PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
303 PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
304 PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
305 PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
306 PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
307 PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
308 PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
309 PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
310 PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
311 PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
312 PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
313 PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
314 PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
315 PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
316 PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
317 PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
318 PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
319 PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
320 PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
321 PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
322 PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
323 PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
324 PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
325};
326
327void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
328{
329 struct pmux_tri_ctlr *pmt =
330 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
331 u32 *tri = &pmt->pmt_ctl[pin];
332 u32 reg;
333
334 /* Error check on pin */
335 assert(pmux_pingrp_isvalid(pin));
336
337 reg = readl(tri);
338 if (enable)
339 reg |= PMUX_TRISTATE_MASK;
340 else
341 reg &= ~PMUX_TRISTATE_MASK;
342 writel(reg, tri);
343}
344
345void pinmux_tristate_enable(enum pmux_pingrp pin)
346{
347 pinmux_set_tristate(pin, 1);
348}
349
350void pinmux_tristate_disable(enum pmux_pingrp pin)
351{
352 pinmux_set_tristate(pin, 0);
353}
354
355void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
356{
357 struct pmux_tri_ctlr *pmt =
358 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
359 u32 *pull = &pmt->pmt_ctl[pin];
360 u32 reg;
361
362 /* Error check on pin and pupd */
363 assert(pmux_pingrp_isvalid(pin));
364 assert(pmux_pin_pupd_isvalid(pupd));
365
366 reg = readl(pull);
367 reg &= ~(0x3 << PMUX_PULL_SHIFT);
368 reg |= (pupd << PMUX_PULL_SHIFT);
369 writel(reg, pull);
370}
371
372void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
373{
374 struct pmux_tri_ctlr *pmt =
375 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
376 u32 *muxctl = &pmt->pmt_ctl[pin];
377 int i, mux = -1;
378 u32 reg;
379
380 /* Error check on pin and func */
381 assert(pmux_pingrp_isvalid(pin));
382 assert(pmux_func_isvalid(func));
383
384 /* Handle special values */
385 if (func == PMUX_FUNC_SAFE)
386 func = tegra_soc_pingroups[pin].func_safe;
387
388 if (func & PMUX_FUNC_RSVD1) {
389 mux = func & 0x3;
390 } else {
391 /* Search for the appropriate function */
392 for (i = 0; i < 4; i++) {
393 if (tegra_soc_pingroups[pin].funcs[i] == func) {
394 mux = i;
395 break;
396 }
397 }
398 }
399 assert(mux != -1);
400
401 reg = readl(muxctl);
402 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
403 reg |= (mux << PMUX_MUXCTL_SHIFT);
404 writel(reg, muxctl);
405
406}
407
408void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
409{
410 struct pmux_tri_ctlr *pmt =
411 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
412 u32 *pin_io = &pmt->pmt_ctl[pin];
413 u32 reg;
414
415 /* Error check on pin and io */
416 assert(pmux_pingrp_isvalid(pin));
417 assert(pmux_pin_io_isvalid(io));
418
419 reg = readl(pin_io);
420 reg &= ~(0x1 << PMUX_IO_SHIFT);
421 reg |= (io & 0x1) << PMUX_IO_SHIFT;
422 writel(reg, pin_io);
423}
424
425static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
426{
427 struct pmux_tri_ctlr *pmt =
428 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
429 u32 *pin_lock = &pmt->pmt_ctl[pin];
430 u32 reg;
431
432 /* Error check on pin and lock */
433 assert(pmux_pingrp_isvalid(pin));
434 assert(pmux_pin_lock_isvalid(lock));
435
436 if (lock == PMUX_PIN_LOCK_DEFAULT)
437 return 0;
438
439 reg = readl(pin_lock);
440 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
441 if (lock == PMUX_PIN_LOCK_ENABLE)
442 reg |= (0x1 << PMUX_LOCK_SHIFT);
443 else {
444 /* lock == DISABLE, which isn't possible */
445 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
446 __func__, lock);
447 }
448 writel(reg, pin_lock);
449
450 return 0;
451}
452
453static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
454{
455 struct pmux_tri_ctlr *pmt =
456 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
457 u32 *pin_od = &pmt->pmt_ctl[pin];
458 u32 reg;
459
460 /* Error check on pin and od */
461 assert(pmux_pingrp_isvalid(pin));
462 assert(pmux_pin_od_isvalid(od));
463
464 if (od == PMUX_PIN_OD_DEFAULT)
465 return 0;
466
467 reg = readl(pin_od);
468 reg &= ~(0x1 << PMUX_OD_SHIFT);
469 if (od == PMUX_PIN_OD_ENABLE)
470 reg |= (0x1 << PMUX_OD_SHIFT);
471 writel(reg, pin_od);
472
473 return 0;
474}
475
476static int pinmux_set_ioreset(enum pmux_pingrp pin,
477 enum pmux_pin_ioreset ioreset)
478{
479 struct pmux_tri_ctlr *pmt =
480 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
481 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
482 u32 reg;
483
484 /* Error check on pin and ioreset */
485 assert(pmux_pingrp_isvalid(pin));
486 assert(pmux_pin_ioreset_isvalid(ioreset));
487
488 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
489 return 0;
490
491 reg = readl(pin_ioreset);
492 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
493 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
494 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
495 writel(reg, pin_ioreset);
496
497 return 0;
498}
499
500void pinmux_config_pingroup(struct pingroup_config *config)
501{
502 enum pmux_pingrp pin = config->pingroup;
503
504 pinmux_set_func(pin, config->func);
505 pinmux_set_pullupdown(pin, config->pull);
506 pinmux_set_tristate(pin, config->tristate);
507 pinmux_set_io(pin, config->io);
508 pinmux_set_lock(pin, config->lock);
509 pinmux_set_od(pin, config->od);
510 pinmux_set_ioreset(pin, config->ioreset);
511}
512
513void pinmux_config_table(struct pingroup_config *config, int len)
514{
515 int i;
516
517 for (i = 0; i < len; i++)
518 pinmux_config_pingroup(&config[i]);
519}
Tom Warren8ca79b22013-03-06 16:16:22 -0700[diff] [blame]520
521static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
522 int slwf)
523{
524 struct pmux_tri_ctlr *pmt =
525 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
526 u32 *pad_slwf = &pmt->pmt_drive[pad];
527 u32 reg;
528
529 /* Error check on pad and slwf */
530 assert(pmux_padgrp_isvalid(pad));
531 assert(pmux_pad_slw_isvalid(slwf));
532
533 /* NONE means unspecified/do not change/use POR value */
534 if (slwf == PGRP_SLWF_NONE)
535 return 0;
536
537 reg = readl(pad_slwf);
538 reg &= ~PGRP_SLWF_MASK;
539 reg |= (slwf << PGRP_SLWF_SHIFT);
540 writel(reg, pad_slwf);
541
542 return 0;
543}
544
545static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
546{
547 struct pmux_tri_ctlr *pmt =
548 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
549 u32 *pad_slwr = &pmt->pmt_drive[pad];
550 u32 reg;
551
552 /* Error check on pad and slwr */
553 assert(pmux_padgrp_isvalid(pad));
554 assert(pmux_pad_slw_isvalid(slwr));
555
556 /* NONE means unspecified/do not change/use POR value */
557 if (slwr == PGRP_SLWR_NONE)
558 return 0;
559
560 reg = readl(pad_slwr);
561 reg &= ~PGRP_SLWR_MASK;
562 reg |= (slwr << PGRP_SLWR_SHIFT);
563 writel(reg, pad_slwr);
564
565 return 0;
566}
567
568static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
569{
570 struct pmux_tri_ctlr *pmt =
571 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
572 u32 *pad_drvup = &pmt->pmt_drive[pad];
573 u32 reg;
574
575 /* Error check on pad and drvup */
576 assert(pmux_padgrp_isvalid(pad));
577 assert(pmux_pad_drv_isvalid(drvup));
578
579 /* NONE means unspecified/do not change/use POR value */
580 if (drvup == PGRP_DRVUP_NONE)
581 return 0;
582
583 reg = readl(pad_drvup);
584 reg &= ~PGRP_DRVUP_MASK;
585 reg |= (drvup << PGRP_DRVUP_SHIFT);
586 writel(reg, pad_drvup);
587
588 return 0;
589}
590
591static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
592{
593 struct pmux_tri_ctlr *pmt =
594 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
595 u32 *pad_drvdn = &pmt->pmt_drive[pad];
596 u32 reg;
597
598 /* Error check on pad and drvdn */
599 assert(pmux_padgrp_isvalid(pad));
600 assert(pmux_pad_drv_isvalid(drvdn));
601
602 /* NONE means unspecified/do not change/use POR value */
603 if (drvdn == PGRP_DRVDN_NONE)
604 return 0;
605
606 reg = readl(pad_drvdn);
607 reg &= ~PGRP_DRVDN_MASK;
608 reg |= (drvdn << PGRP_DRVDN_SHIFT);
609 writel(reg, pad_drvdn);
610
611 return 0;
612}
613
614static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
615{
616 struct pmux_tri_ctlr *pmt =
617 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
618 u32 *pad_lpmd = &pmt->pmt_drive[pad];
619 u32 reg;
620
621 /* Error check pad and lpmd value */
622 assert(pmux_padgrp_isvalid(pad));
623 assert(pmux_pad_lpmd_isvalid(lpmd));
624
625 /* NONE means unspecified/do not change/use POR value */
626 if (lpmd == PGRP_LPMD_NONE)
627 return 0;
628
629 reg = readl(pad_lpmd);
630 reg &= ~PGRP_LPMD_MASK;
631 reg |= (lpmd << PGRP_LPMD_SHIFT);
632 writel(reg, pad_lpmd);
633
634 return 0;
635}
636
637static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
638{
639 struct pmux_tri_ctlr *pmt =
640 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
641 u32 *pad_schmt = &pmt->pmt_drive[pad];
642 u32 reg;
643
644 /* Error check pad */
645 assert(pmux_padgrp_isvalid(pad));
646
647 reg = readl(pad_schmt);
648 reg &= ~(1 << PGRP_SCHMT_SHIFT);
649 if (schmt == PGRP_SCHMT_ENABLE)
650 reg |= (0x1 << PGRP_SCHMT_SHIFT);
651 writel(reg, pad_schmt);
652
653 return 0;
654}
655static int padgrp_set_hsm(enum pdrive_pingrp pad,
656 enum pgrp_hsm hsm)
657{
658 struct pmux_tri_ctlr *pmt =
659 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
660 u32 *pad_hsm = &pmt->pmt_drive[pad];
661 u32 reg;
662
663 /* Error check pad */
664 assert(pmux_padgrp_isvalid(pad));
665
666 reg = readl(pad_hsm);
667 reg &= ~(1 << PGRP_HSM_SHIFT);
668 if (hsm == PGRP_HSM_ENABLE)
669 reg |= (0x1 << PGRP_HSM_SHIFT);
670 writel(reg, pad_hsm);
671
672 return 0;
673}
674
675void padctrl_config_pingroup(struct padctrl_config *config)
676{
677 enum pdrive_pingrp pad = config->padgrp;
678
679 padgrp_set_drvup_slwf(pad, config->slwf);
680 padgrp_set_drvdn_slwr(pad, config->slwr);
681 padgrp_set_drvup(pad, config->drvup);
682 padgrp_set_drvdn(pad, config->drvdn);
683 padgrp_set_lpmd(pad, config->lpmd);
684 padgrp_set_schmt(pad, config->schmt);
685 padgrp_set_hsm(pad, config->hsm);
686}
687
688void padgrp_config_table(struct padctrl_config *config, int len)
689{
690 int i;
691
692 for (i = 0; i < len; i++)
693 padctrl_config_pingroup(&config[i]);
694}