blob: 509c671cda757669d4877ed017f9120901d4e103 [file] [log] [blame]
Marek Vasutaa04fef2013-08-31 15:53:45 +02001/*
2 * Creative ZEN X-Fi3 board
3 *
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
5 *
6 * Hardware investigation done by:
7 *
8 * Amaury Pouly <amaury.pouly@gmail.com>
9 *
10 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#include <common.h>
14#include <errno.h>
15#include <asm/gpio.h>
16#include <asm/io.h>
17#include <asm/arch/iomux-mx23.h>
18#include <asm/arch/imx-regs.h>
19#include <asm/arch/clock.h>
20#include <asm/arch/sys_proto.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24/*
25 * Functions
26 */
27int board_early_init_f(void)
28{
29 /* IO0 clock at 480MHz */
30 mxs_set_ioclk(MXC_IOCLK0, 480000);
31
32 /* SSP0 clock at 96MHz */
33 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
34
35 return 0;
36}
37
38int dram_init(void)
39{
40 return mxs_dram_init();
41}
42
43#ifdef CONFIG_CMD_MMC
44static int xfi3_mmc_cd(int id)
45{
46 switch (id) {
47 case 0:
48 /* The SSP_DETECT is inverted on this board. */
49 return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
50 case 1:
51 /* Phison bridge always present */
52 return 1;
53 default:
54 return 0;
55 }
56}
57
58int board_mmc_init(bd_t *bis)
59{
60 int ret;
61
62 /* MicroSD slot */
63 gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
64 gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
65 ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
66 if (ret)
67 return ret;
68
69 /* Phison SD-NAND bridge */
70 ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
71
72 return ret;
73}
74#endif
75
76#ifdef CONFIG_VIDEO_MXS
77static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
78{
79 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
80 const unsigned int timeout = 0x10000;
81
82 if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
83 timeout))
84 return -ETIMEDOUT;
85
86 writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
87 (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
88 &regs->hw_lcdif_transfer_count);
89
90 writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
91 &regs->hw_lcdif_ctrl_clr);
92
93 if (data)
94 writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set);
95
96 writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
97
98 if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29,
99 timeout))
100 return -ETIMEDOUT;
101
102 writel(payload, &regs->hw_lcdif_data);
103 return mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
104 timeout);
105}
106
107static void mxsfb_write_register(uint32_t reg, uint32_t data)
108{
109 mxsfb_write_byte(reg, 0);
110 mxsfb_write_byte(data, 1);
111}
112
113static const struct {
114 uint8_t reg;
115 uint8_t delay;
116 uint16_t val;
117} lcd_regs[] = {
118 { 0x01, 0, 0x001c },
119 { 0x02, 0, 0x0100 },
120 /* Writing 0x30 to reg. 0x03 flips the LCD */
121 { 0x03, 0, 0x1038 },
122 { 0x08, 0, 0x0808 },
123 /* This can contain 0x111 to rotate the LCD. */
124 { 0x0c, 0, 0x0000 },
125 { 0x0f, 0, 0x0c01 },
126 { 0x20, 0, 0x0000 },
127 { 0x21, 30, 0x0000 },
128 /* Wait 30 mS here */
129 { 0x10, 0, 0x0a00 },
130 { 0x11, 30, 0x1038 },
131 /* Wait 30 mS here */
132 { 0x12, 0, 0x1010 },
133 { 0x13, 0, 0x0050 },
134 { 0x14, 0, 0x4f58 },
135 { 0x30, 0, 0x0000 },
136 { 0x31, 0, 0x00db },
137 { 0x32, 0, 0x0000 },
138 { 0x33, 0, 0x0000 },
139 { 0x34, 0, 0x00db },
140 { 0x35, 0, 0x0000 },
141 { 0x36, 0, 0x00af },
142 { 0x37, 0, 0x0000 },
143 { 0x38, 0, 0x00db },
144 { 0x39, 0, 0x0000 },
145 { 0x50, 0, 0x0000 },
146 { 0x51, 0, 0x0705 },
147 { 0x52, 0, 0x0e0a },
148 { 0x53, 0, 0x0300 },
149 { 0x54, 0, 0x0a0e },
150 { 0x55, 0, 0x0507 },
151 { 0x56, 0, 0x0000 },
152 { 0x57, 0, 0x0003 },
153 { 0x58, 0, 0x090a },
154 { 0x59, 30, 0x0a09 },
155 /* Wait 30 mS here */
156 { 0x07, 30, 0x1017 },
157 /* Wait 40 mS here */
158 { 0x36, 0, 0x00af },
159 { 0x37, 0, 0x0000 },
160 { 0x38, 0, 0x00db },
161 { 0x39, 0, 0x0000 },
162 { 0x20, 0, 0x0000 },
163 { 0x21, 0, 0x0000 },
164};
165
Peng Fand39c3462015-10-29 15:54:40 +0800166void mxsfb_system_setup(void)
Marek Vasutaa04fef2013-08-31 15:53:45 +0200167{
168 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
169 int i;
170
171 /* Switch the LCDIF into System-Mode */
172 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
173 LCDIF_CTRL_BYPASS_COUNT, &regs->hw_lcdif_ctrl_clr);
174
175 /* Restart the SmartLCD controller */
176 mdelay(50);
177 writel(1, &regs->hw_lcdif_ctrl1_set);
178 mdelay(50);
179 writel(1, &regs->hw_lcdif_ctrl1_clr);
180 mdelay(50);
181 writel(1, &regs->hw_lcdif_ctrl1_set);
182 mdelay(50);
183
184 /* Program the SmartLCD controller */
185 writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, &regs->hw_lcdif_ctrl1_set);
186
187 writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
188 (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
189 (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
190 (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
191 &regs->hw_lcdif_timing);
192
193 /*
194 * OTM2201A init and configuration sequence.
195 */
196 for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
197 mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
198 if (lcd_regs[i].delay)
199 mdelay(lcd_regs[i].delay);
200 }
201 /* Turn on Framebuffer Upload Mode */
202 mxsfb_write_byte(0x22, 0);
203
204 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
205 &regs->hw_lcdif_ctrl_set);
206}
207#endif
208
209int board_init(void)
210{
211 /* Adress of boot parameters */
212 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
213
214 /* Turn on PWM backlight */
215 gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
216
217 return 0;
218}
219
220int board_eth_init(bd_t *bis)
221{
222 usb_eth_initialize(bis);
223 return 0;
224}