| Ricardo Ribalda Delgado | 1f4d532 | 2008-10-21 18:29:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2008 |
| Ricardo Ribalda Delgado | 5b218ae | 2016-01-26 11:24:08 +0100 | [diff] [blame] | 3 | * Ricado Ribalda-Universidad Autonoma de Madrid-ricardo.ribalda@gmail.com |
| Ricardo Ribalda Delgado | 1f4d532 | 2008-10-21 18:29:46 +0200 | [diff] [blame] | 4 | * This work has been supported by: QTechnology http://qtec.com/ |
| 5 | * based on xparameters-ml507.h by Xilinx |
| 6 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| Ricardo Ribalda Delgado | 1f4d532 | 2008-10-21 18:29:46 +0200 | [diff] [blame] | 8 | */ |
| 9 | |
| 10 | #ifndef XPARAMETER_H |
| 11 | #define XPARAMETER_H |
| 12 | |
| 13 | #define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000 |
| 14 | #define XPAR_IIC_EEPROM_BASEADDR 0x81600000 |
| 15 | #define XPAR_INTC_0_BASEADDR 0x81800000 |
| 16 | #define XPAR_SPI_0_BASEADDR 0x83400000 |
| Ricardo Ribalda Delgado | 1f4d532 | 2008-10-21 18:29:46 +0200 | [diff] [blame] | 17 | #define XPAR_FLASH_MEM0_BASEADDR 0xFE000000 |
| 18 | #define XPAR_PLB_CLOCK_FREQ_HZ 100000000 |
| 19 | #define XPAR_CORE_CLOCK_FREQ_HZ 400000000 |
| Ricardo Ribalda Delgado | 6a2c1aa | 2016-01-26 11:24:15 +0100 | [diff] [blame] | 20 | #define XPAR_INTC_MAX_NUM_INTR_INPUTS 32 |
| Ricardo Ribalda Delgado | 1f4d532 | 2008-10-21 18:29:46 +0200 | [diff] [blame] | 21 | #define XPAR_SPI_0_NUM_TRANSFER_BITS 8 |
| Ricardo Ribalda Delgado | 6a2c1aa | 2016-01-26 11:24:15 +0100 | [diff] [blame] | 22 | #define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000 |
| Ricardo Ribalda Delgado | 1f4d532 | 2008-10-21 18:29:46 +0200 | [diff] [blame] | 23 | |
| 24 | #endif |