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Mike Frysinger8b219cf2008-10-12 21:54:07 -04001/*
2 * U-boot - Configuration file for cm-bf548 board
3 */
4
5#ifndef __CONFIG_CM_BF548_H__
6#define __CONFIG_CM_BF548_H__
7
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysinger8b219cf2008-10-12 21:54:07 -04009
10
11/*
12 * Processor Settings
13 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050014#define CONFIG_BFIN_CPU bf548-0.0
Mike Frysinger8b219cf2008-10-12 21:54:07 -040015#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
16
17
18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 25000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 21
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 4
40
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -040041/* Decrease core voltage */
42#define CONFIG_VR_CTL_VAL (VLEV_115 | GAIN_20 | FREQ_1000)
43
Mike Frysinger8b219cf2008-10-12 21:54:07 -040044
45/*
46 * Memory Settings
47 */
48#define CONFIG_MEM_ADD_WDTH 10
49#define CONFIG_MEM_SIZE 64
50
51#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
52#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
53#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
54
55/* Default bank mapping:
56 * Async Bank 0 - 32MB Burst Flash
57 * Async Bank 1 - Ethernet
58 * Async Bank 2 - Nothing
59 * Async Bank 3 - Nothing
60 */
61#define CONFIG_EBIU_AMGCTL_VAL 0xFF
62#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
63#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
64#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
65#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
66
Mike Frysinger98ae6072010-08-02 16:30:39 -040067#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
Mike Frysinger8b219cf2008-10-12 21:54:07 -040068#define CONFIG_SYS_MALLOC_LEN (640 * 1024)
69
70
71/*
72 * Network Settings
73 */
74#define ADI_CMDS_NETWORK 1
Ben Warren736fead2009-07-20 22:01:11 -070075#define CONFIG_SMC911X 1
76#define CONFIG_SMC911X_BASE 0x24000000
77#define CONFIG_SMC911X_16_BIT
Mike Frysinger8b219cf2008-10-12 21:54:07 -040078#define CONFIG_HOSTNAME cm-bf548
79/* Uncomment next line to use fixed MAC address */
80/* #define CONFIG_ETHADDR 02:80:ad:24:31:91 */
81
82
83/*
84 * Flash Settings
85 */
86#define CONFIG_FLASH_CFI_DRIVER
87#define CONFIG_SYS_FLASH_BASE 0x20000000
88#define CONFIG_SYS_FLASH_CFI
89#define CONFIG_SYS_FLASH_PROTECTION
90#define CONFIG_SYS_MAX_FLASH_BANKS 1
91#define CONFIG_SYS_MAX_FLASH_SECT 259
92
93
94/*
95 * Env Storage Settings
96 */
97#define CONFIG_ENV_IS_IN_FLASH 1
98#define CONFIG_ENV_ADDR 0x20008000
99#define CONFIG_ENV_OFFSET 0x8000
100#define CONFIG_ENV_SIZE 0x8000
Mike Frysinger76d82182009-07-21 22:17:36 -0400101#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Mike Frysinger8b219cf2008-10-12 21:54:07 -0400102
103
104/*
105 * I2C Settings
106 */
107#define CONFIG_BFIN_TWI_I2C 1
108#define CONFIG_HARD_I2C 1
Mike Frysinger8b219cf2008-10-12 21:54:07 -0400109
110
111/*
112 * Misc Settings
113 */
114#define CONFIG_BAUDRATE 115200
115#define CONFIG_BOARD_EARLY_INIT_F
116#define CONFIG_RTC_BFIN
117#define CONFIG_UART_CONSOLE 1
Harald Krapfenbauerfd04a052009-10-14 08:37:32 -0400118#define CONFIG_BOOTCOMMAND "run flashboot"
119#define FLASHBOOT_ENV_SETTINGS "flashboot=bootm 0x20040000\0"
Masahiro Yamadae91df492014-03-05 16:59:37 +0900120#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
Mike Frysinger8b219cf2008-10-12 21:54:07 -0400121
Sonic Zhange45eb6b2013-11-18 14:01:38 +0800122#define CONFIG_ADI_GPIO2
123
Mike Frysinger8b219cf2008-10-12 21:54:07 -0400124#ifndef __ADSPBF542__
125/* Don't waste time transferring a logo over the UART */
126# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
127# define CONFIG_VIDEO
Mike Frysinger42c6e9a2012-02-03 20:44:54 -0500128# define EASYLOGO_HEADER <asm/bfin_logo_230x230_gzip.h>
Mike Frysinger8b219cf2008-10-12 21:54:07 -0400129# endif
130# define CONFIG_DEB_DMA_URGENT
131#endif
132
133/* Define if want to do post memory test */
134#undef CONFIG_POST
135#ifdef CONFIG_POST
136#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
137#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
138#endif
139
140
141/*
142 * Pull in common ADI header for remaining command/environment setup
143 */
144#include <configs/bfin_adi_common.h>
145
Mike Frysinger8b219cf2008-10-12 21:54:07 -0400146#endif