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Gary Jennejohn73ccb342008-04-28 14:04:32 +02001/*
2 * (C) Copyright 2008
3 * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Gary Jennejohn73ccb342008-04-28 14:04:32 +02006 */
7
8/************************************************************************
9 * quad100hd.h - configuration for Quad100hd board
10 ***********************************************************************/
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*-----------------------------------------------------------------------
15 * High Level Configuration Options
16 *----------------------------------------------------------------------*/
17#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
Gary Jennejohn73ccb342008-04-28 14:04:32 +020018#define CONFIG_405EP 1 /* Specifc 405EP support*/
19
Wolfgang Denk2ae18242010-10-06 09:05:45 +020020#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
21
Gary Jennejohn73ccb342008-04-28 14:04:32 +020022#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
23
24#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
25
26#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
27#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
28
Gary Jennejohn0c119352008-05-14 13:39:22 +020029/* the environment is in the EEPROM by default */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +020030#define CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020031#undef CONFIG_ENV_IS_IN_FLASH
Gary Jennejohn73ccb342008-04-28 14:04:32 +020032
Ben Warren96e21f82008-10-27 23:50:15 -070033#define CONFIG_PPC4xx_EMAC
Gary Jennejohn73ccb342008-04-28 14:04:32 +020034#define CONFIG_HAS_ETH1 1
35#define CONFIG_MII 1 /* MII PHY management */
36#define CONFIG_PHY_ADDR 0x01 /* PHY address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
Gary Jennejohn73ccb342008-04-28 14:04:32 +020038#define CONFIG_PHY_RESET 1
39#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
40
41/*
42 * Command line configuration.
43 */
44#include <config_cmd_default.h>
45
46#undef CONFIG_CMD_ASKENV
47#undef CONFIG_CMD_CACHE
48#define CONFIG_CMD_DHCP
49#undef CONFIG_CMD_DIAG
50#define CONFIG_CMD_EEPROM
51#undef CONFIG_CMD_ELF
52#define CONFIG_CMD_I2C
53#undef CONFIG_CMD_IRQ
54#define CONFIG_CMD_JFFS2
Gary Jennejohn73ccb342008-04-28 14:04:32 +020055#undef CONFIG_CMD_MII
56#define CONFIG_CMD_NAND
57#undef CONFIG_CMD_PING
58#define CONFIG_CMD_REGINFO
59
60#undef CONFIG_WATCHDOG /* watchdog disabled */
61
62/*-----------------------------------------------------------------------
63 * SDRAM
64 *----------------------------------------------------------------------*/
65/*
66 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
67 */
68#define CONFIG_SDRAM_BANK0 1
Gary Jennejohn73ccb342008-04-28 14:04:32 +020069
70/* FIX! SDRAM timings used in datasheet */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
72#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
73#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
74#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
75#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
Gary Jennejohn73ccb342008-04-28 14:04:32 +020076
77/*
78 * JFFS2
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_JFFS2_FIRST_BANK 0
81#ifdef CONFIG_SYS_KERNEL_IN_JFFS2
82#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
Gary Jennejohn73ccb342008-04-28 14:04:32 +020083#else /* kernel not in JFFS */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
Gary Jennejohn73ccb342008-04-28 14:04:32 +020085#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_JFFS2_NUM_BANKS 1
Gary Jennejohn73ccb342008-04-28 14:04:32 +020087
88/*-----------------------------------------------------------------------
89 * Serial Port
90 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020091#define CONFIG_CONS_INDEX 1 /* Use UART0 */
92#define CONFIG_SYS_NS16550
93#define CONFIG_SYS_NS16550_SERIAL
94#define CONFIG_SYS_NS16550_REG_SIZE 1
95#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
97#define CONFIG_SYS_BASE_BAUD 691200
Gary Jennejohn73ccb342008-04-28 14:04:32 +020098#define CONFIG_BAUDRATE 115200
Gary Jennejohn73ccb342008-04-28 14:04:32 +020099
100/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CONFIG_SYS_BAUDRATE_TABLE \
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200102 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
103
104/*-----------------------------------------------------------------------
105 * Miscellaneous configurable options
106 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_LONGHELP /* undef to save memory */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200108#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200110#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200112#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
114#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
115#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
118#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
121#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200122
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200123#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200125
126#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
127#define CONFIG_LOOPW 1 /* enable loopw command */
128#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
129#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
130#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
131
132/*-----------------------------------------------------------------------
133 * I2C
134 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000135#define CONFIG_SYS_I2C
136#define CONFIG_SYS_I2C_PPC4XX
137#define CONFIG_SYS_I2C_PPC4XX_CH0
138#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
139#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
142#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
145#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
146#define CONFIG_SYS_EEPROM_SIZE 0x2000
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200147
148/*-----------------------------------------------------------------------
149 * Start addresses for the final memory configuration
150 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_SDRAM_BASE 0x00000000
154#define CONFIG_SYS_FLASH_BASE 0xFFC00000
155#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
156#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200157#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200158
159/*
160 * For booting Linux, the board info and command line data
161 * have to be in the first 8 MB of memory, since this is
162 * the maximum mapped by the Linux kernel during initialization.
163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200165
166/*-----------------------------------------------------------------------
167 * FLASH organization
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200170#define CONFIG_FLASH_CFI_DRIVER
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
175#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
178#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
181#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
184#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200185
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200186#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200187#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
Gary Jennejohn0c119352008-05-14 13:39:22 +0200188/* the environment is located before u-boot */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200189#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
Gary Jennejohn0c119352008-05-14 13:39:22 +0200190
191/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200192#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
193#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200194#endif
195
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200196#ifdef CONFIG_ENV_IS_IN_EEPROM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200197#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
198#define CONFIG_ENV_OFFSET 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200200#endif
201
202/* partly from PPCBoot */
203/* NAND */
204#define CONFIG_NAND
205#ifdef CONFIG_NAND
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_NAND_BASE 0x60000000
207#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
208#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
209#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
210#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
211#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MAX_NAND_DEVICE 1
Wolfgang Denk170c1972009-07-18 15:32:10 +0200213
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200214#endif
215
216/*-----------------------------------------------------------------------
217 * Definitions for initial stack pointer and data area (in data cache)
218 */
219/* use on chip memory (OCM) for temperary stack until sdram is tested */
Stefan Roesea47a12b2010-04-15 16:07:28 +0200220/* see ./arch/powerpc/cpu/ppc4xx/start.S */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_TEMP_STACK_OCM 1
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200222
223/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
225#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
226#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200227#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200228
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200229#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200231
232/*-----------------------------------------------------------------------
233 * External Bus Controller (EBC) Setup
234 * Taken from PPCBoot board/icecube/icecube.h
235 */
236
Stefan Roesea47a12b2010-04-15 16:07:28 +0200237/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_EBC_PB0AP 0x04002480
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200239/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
241#define CONFIG_SYS_EBC_PB1AP 0x04005480
242#define CONFIG_SYS_EBC_PB1CR 0x60018000
243#define CONFIG_SYS_EBC_PB2AP 0x00000000
244#define CONFIG_SYS_EBC_PB2CR 0x00000000
245#define CONFIG_SYS_EBC_PB3AP 0x00000000
246#define CONFIG_SYS_EBC_PB3CR 0x00000000
247#define CONFIG_SYS_EBC_PB4AP 0x00000000
248#define CONFIG_SYS_EBC_PB4CR 0x00000000
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200249
250/*-----------------------------------------------------------------------
251 * Definitions for GPIO setup (PPC405EP specific)
252 *
253 * Taken in part from PPCBoot board/icecube/icecube.h
254 */
Stefan Roesea47a12b2010-04-15 16:07:28 +0200255/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
Stefan Roeseafabb492010-09-12 06:21:37 +0200256#define CONFIG_SYS_GPIO0_OSRL 0x55555550
257#define CONFIG_SYS_GPIO0_OSRH 0x00000110
258#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
259#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200261#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
263#define CONFIG_SYS_GPIO0_ODR 0x00000000
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200264
265#if defined(CONFIG_CMD_KGDB)
266#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Gary Jennejohn73ccb342008-04-28 14:04:32 +0200267#endif
268
269/* ENVIRONMENT VARS */
270
271#define CONFIG_IPADDR 192.168.1.67
272#define CONFIG_SERVERIP 192.168.1.50
273#define CONFIG_GATEWAYIP 192.168.1.1
274#define CONFIG_NETMASK 255.255.255.0
275#define CONFIG_LOADADDR 300000
276#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
277
278/* pass open firmware flat tree */
279#define CONFIG_OF_LIBFDT 1
280
281#endif /* __CONFIG_H */