blob: c2899ef2ea64d317e6f4e1692b30e43785775c85 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Alexey Brodkin01496c42015-03-17 14:55:14 +03002/*
Alexey Brodkin9515e412019-12-26 13:46:27 +03003 * Copyright (C) 2015-2016, 2020 Synopsys, Inc. (www.synopsys.com)
Alexey Brodkin01496c42015-03-17 14:55:14 +03004 */
5/dts-v1/;
6
7#include "skeleton.dtsi"
8
9/ {
Alexey Brodkinc3dcd502018-10-02 11:37:25 +030010 model = "snps,nsim";
11
Alexey Brodkin01496c42015-03-17 14:55:14 +030012 aliases {
Alexey Brodkin9515e412019-12-26 13:46:27 +030013 console = &uart0;
Alexey Brodkin01496c42015-03-17 14:55:14 +030014 };
15
Vlad Zakharov0c770922017-03-21 14:49:48 +030016 cpu_card {
17 core_clk: core_clk {
18 #clock-cells = <0>;
19 compatible = "fixed-clock";
20 clock-frequency = <70000000>;
21 u-boot,dm-pre-reloc;
22 };
23 };
24
Alexey Brodkin9515e412019-12-26 13:46:27 +030025 uart0: serial@f0000000 {
26 compatible = "snps,dw-apb-uart";
27 reg = <0xf0000000 0x1000>;
28 reg-shift = <2>;
29 reg-io-width = <4>;
Vlad Zakharov0c770922017-03-21 14:49:48 +030030 clock-frequency = <70000000>;
Alexey Brodkin01496c42015-03-17 14:55:14 +030031 };
32
Alexey Brodkin95f71032019-12-26 14:47:42 +030033 virtio0: virtio@f0100000 {
34 compatible = "virtio,mmio";
35 reg = <0xf0100000 0x2000>;
36 };
37
38 virtio1: virtio@f0102000 {
39 compatible = "virtio,mmio";
40 reg = <0xf0102000 0x2000>;
41 };
42
43 virtio2: virtio@f0104000 {
44 compatible = "virtio,mmio";
45 reg = <0xf0104000 0x2000>;
46 };
47
48 virtio3: virtio@f0106000 {
49 compatible = "virtio,mmio";
50 reg = <0xf0106000 0x2000>;
51 };
52
53 virtio4: virtio@f0108000 {
54 compatible = "virtio,mmio";
55 reg = <0xf0108000 0x2000>;
56 };
Alexey Brodkin01496c42015-03-17 14:55:14 +030057};