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Ajay Bhargav0c442292011-08-22 17:57:38 +05301/*
2 * (C) Copyright 2011
3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
5 *
6 * (C) Copyright 2010
7 * Marvell Semiconductor <www.marvell.com>
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Ajay Bhargav0c442292011-08-22 17:57:38 +053010 */
11
12#ifndef __MVGPIO_H__
13#define __MVGPIO_H__
14
15#include <common.h>
16
17#ifdef CONFIG_SHEEVA_88SV331xV5
18/*
19 * GPIO Register map for SHEEVA 88SV331xV5
20 */
21struct gpio_reg {
22 u32 gplr; /* Pin Level Register - 0x0000 */
23 u32 pad0[2];
24 u32 gpdr; /* Pin Direction Register - 0x000C */
25 u32 pad1[2];
26 u32 gpsr; /* Pin Output Set Register - 0x0018 */
27 u32 pad2[2];
28 u32 gpcr; /* Pin Output Clear Register - 0x0024 */
29 u32 pad3[2];
30 u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
31 u32 pad4[2];
32 u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
33 u32 pad5[2];
34 u32 gedr; /* Edge Detect Status Register - 0x0048 */
35 u32 pad6[2];
36 u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
37 u32 pad7[2];
38 u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
39 u32 pad8[2];
40 u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
41 Register - 0x006C */
42 u32 pad9[2];
43 u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
44 Register - 0x0078 */
45 u32 pad10[2];
46 u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
47 Register - 0x0084 */
48 u32 pad11[2];
49 u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
50 Register - 0x0090 */
51 u32 pad12[2];
52 u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
53};
54#else
55#error "CPU core subversion not defined"
56#endif
57
58#endif /* __MVGPIO_H__ */