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wdenk7a8e9bed2003-05-31 18:35:21 +00001/*
2 * (C) Copyright 2002
3 * Daniel Engström, Omicron Ceti AB, daniel@omicron.se
wdenk8bde7f72003-06-27 21:31:46 +00004 *
wdenk7a8e9bed2003-05-31 18:35:21 +00005 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Alex Zuepke <azu@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#include <common.h>
29#include <asm/io.h>
30
31ulong myflush(void);
32
33
34#define SC520_MAX_FLASH_BANKS 3
35#define SC520_FLASH_BANK0_BASE 0x38000000 /* BOOTCS */
36#define SC520_FLASH_BANK1_BASE 0x30000000 /* ROMCS0 */
37#define SC520_FLASH_BANK2_BASE 0x28000000 /* ROMCS1 */
38#define SC520_FLASH_BANKSIZE 0x8000000
39
40#define AMD29LV016_SIZE 0x200000
41#define AMD29LV016_SECTORS 32
42
43flash_info_t flash_info[SC520_MAX_FLASH_BANKS];
44
45#define CMD_READ_ARRAY 0x00F000F0
46#define CMD_UNLOCK1 0x00AA00AA
47#define CMD_UNLOCK2 0x00550055
48#define CMD_ERASE_SETUP 0x00800080
49#define CMD_ERASE_CONFIRM 0x00300030
50#define CMD_PROGRAM 0x00A000A0
51#define CMD_UNLOCK_BYPASS 0x00200020
52
53
54#define BIT_ERASE_DONE 0x00800080
55#define BIT_RDY_MASK 0x00800080
56#define BIT_PROGRAM_ERROR 0x00200020
57#define BIT_TIMEOUT 0x80000000 /* our flag */
58
59#define READY 1
60#define ERR 2
61#define TMO 4
62
63/*-----------------------------------------------------------------------
64 */
65
66ulong flash_init(void)
67{
68 int i, j;
69 ulong size = 0;
wdenk8bde7f72003-06-27 21:31:46 +000070
wdenk7a8e9bed2003-05-31 18:35:21 +000071 for (i = 0; i < SC520_MAX_FLASH_BANKS; i++) {
72 ulong flashbase = 0;
wdenk8bde7f72003-06-27 21:31:46 +000073 int sectsize = 0;
wdenk7a8e9bed2003-05-31 18:35:21 +000074 if (i==0 || i==2) {
wdenk8bde7f72003-06-27 21:31:46 +000075 /* FixMe: this assumes that bank 0 and 2
wdenk7a8e9bed2003-05-31 18:35:21 +000076 * are mapped to the two 8Mb banks */
77 flash_info[i].flash_id =
78 (AMD_MANUFACT & FLASH_VENDMASK) |
79 (AMD_ID_LV016B & FLASH_TYPEMASK);
wdenk8bde7f72003-06-27 21:31:46 +000080
wdenk7a8e9bed2003-05-31 18:35:21 +000081 flash_info[i].size = AMD29LV016_SIZE*4;
82 flash_info[i].sector_count = AMD29LV016_SECTORS;
83 sectsize = (AMD29LV016_SIZE*4)/AMD29LV016_SECTORS;
84 } else {
wdenk8bde7f72003-06-27 21:31:46 +000085 /* FixMe: this assumes that bank1 is unmapped
wdenk7a8e9bed2003-05-31 18:35:21 +000086 * (or mapped to the same flash bank as BOOTCS) */
87 flash_info[i].flash_id = 0;
88 flash_info[i].size = 0;
89 flash_info[i].sector_count = 0;
90 sectsize=0;
91 }
92 memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
93 switch (i) {
94 case 0:
95 flashbase = SC520_FLASH_BANK0_BASE;
96 break;
97 case 1:
98 flashbase = SC520_FLASH_BANK1_BASE;
99 break;
100 case 2:
101 flashbase = SC520_FLASH_BANK0_BASE;
102 break;
103 default:
wdenk5f535fe2003-09-18 09:21:33 +0000104 panic("configured too many flash banks!\n");
wdenk7a8e9bed2003-05-31 18:35:21 +0000105 }
wdenk8bde7f72003-06-27 21:31:46 +0000106
wdenk7a8e9bed2003-05-31 18:35:21 +0000107 for (j = 0; j < flash_info[i].sector_count; j++) {
108 flash_info[i].start[j] = sectsize;
109 flash_info[i].start[j] = flashbase + j * sectsize;
110 }
111 size += flash_info[i].size;
112 }
wdenk8bde7f72003-06-27 21:31:46 +0000113
wdenk7a8e9bed2003-05-31 18:35:21 +0000114 /*
115 * Protect monitor and environment sectors
116 */
117 flash_protect(FLAG_PROTECT_SET,
118 i386boot_start-SC520_FLASH_BANK0_BASE,
119 i386boot_end-SC520_FLASH_BANK0_BASE,
120 &flash_info[0]);
wdenk8bde7f72003-06-27 21:31:46 +0000121
wdenk7a8e9bed2003-05-31 18:35:21 +0000122#ifdef CFG_ENV_ADDR
123 flash_protect(FLAG_PROTECT_SET,
124 CFG_ENV_ADDR,
125 CFG_ENV_ADDR + CFG_ENV_SIZE - 1,
126 &flash_info[0]);
127#endif
128 return size;
129}
130
131/*-----------------------------------------------------------------------
132 */
133void flash_print_info(flash_info_t *info)
134{
135 int i;
136
137 switch (info->flash_id & FLASH_VENDMASK) {
138 case (AMD_MANUFACT & FLASH_VENDMASK):
139 printf("AMD: ");
140 break;
141 default:
142 printf("Unknown Vendor ");
143 break;
144 }
wdenk8bde7f72003-06-27 21:31:46 +0000145
wdenk7a8e9bed2003-05-31 18:35:21 +0000146 switch (info->flash_id & FLASH_TYPEMASK) {
147 case (AMD_ID_LV016B & FLASH_TYPEMASK):
148 printf("4x Amd29LV016B (16Mbit)\n");
149 break;
150 default:
151 printf("Unknown Chip Type\n");
152 goto done;
153 break;
154 }
wdenk8bde7f72003-06-27 21:31:46 +0000155
wdenk7a8e9bed2003-05-31 18:35:21 +0000156 printf(" Size: %ld MB in %d Sectors\n",
157 info->size >> 20, info->sector_count);
wdenk8bde7f72003-06-27 21:31:46 +0000158
wdenk7a8e9bed2003-05-31 18:35:21 +0000159 printf(" Sector Start Addresses:");
160 for (i = 0; i < info->sector_count; i++) {
161 if ((i % 5) == 0) {
162 printf ("\n ");
163 }
164 printf (" %08lX%s", info->start[i],
165 info->protect[i] ? " (RO)" : " ");
166 }
167 printf ("\n");
wdenk8bde7f72003-06-27 21:31:46 +0000168
wdenk7a8e9bed2003-05-31 18:35:21 +0000169 done:
170}
171
172/*-----------------------------------------------------------------------
173 */
174
175int flash_erase(flash_info_t *info, int s_first, int s_last)
176{
177 ulong result;
178 int iflag, prot, sect;
179 int rc = ERR_OK;
180 int chip1, chip2;
181
182 /* first look for protection bits */
wdenk8bde7f72003-06-27 21:31:46 +0000183
wdenk7a8e9bed2003-05-31 18:35:21 +0000184 if (info->flash_id == FLASH_UNKNOWN) {
185 return ERR_UNKNOWN_FLASH_TYPE;
186 }
wdenk8bde7f72003-06-27 21:31:46 +0000187
wdenk7a8e9bed2003-05-31 18:35:21 +0000188 if ((s_first < 0) || (s_first > s_last)) {
189 return ERR_INVAL;
190 }
wdenk8bde7f72003-06-27 21:31:46 +0000191
wdenk7a8e9bed2003-05-31 18:35:21 +0000192 if ((info->flash_id & FLASH_VENDMASK) !=
193 (AMD_MANUFACT & FLASH_VENDMASK)) {
194 return ERR_UNKNOWN_FLASH_VENDOR;
195 }
wdenk8bde7f72003-06-27 21:31:46 +0000196
wdenk7a8e9bed2003-05-31 18:35:21 +0000197 prot = 0;
198 for (sect=s_first; sect<=s_last; ++sect) {
199 if (info->protect[sect]) {
200 prot++;
201 }
202 }
203 if (prot) {
204 return ERR_PROTECTED;
205 }
wdenk8bde7f72003-06-27 21:31:46 +0000206
wdenk7a8e9bed2003-05-31 18:35:21 +0000207 /*
208 * Disable interrupts which might cause a timeout
209 * here. Remember that our exception vectors are
210 * at address 0 in the flash, and we don't want a
211 * (ticker) exception to happen while the flash
212 * chip is in programming mode.
213 */
214 iflag = disable_interrupts();
wdenk8bde7f72003-06-27 21:31:46 +0000215
wdenk7a8e9bed2003-05-31 18:35:21 +0000216 /* Start erase on unprotected sectors */
217 for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
218 printf("Erasing sector %2d ... ", sect);
wdenk8bde7f72003-06-27 21:31:46 +0000219
wdenk7a8e9bed2003-05-31 18:35:21 +0000220 /* arm simple, non interrupt dependent timer */
221 reset_timer();
wdenk8bde7f72003-06-27 21:31:46 +0000222
223 if (info->protect[sect] == 0) {
wdenk7a8e9bed2003-05-31 18:35:21 +0000224 /* not protected */
225 ulong addr = info->start[sect];
wdenk8bde7f72003-06-27 21:31:46 +0000226
wdenk7a8e9bed2003-05-31 18:35:21 +0000227 writel(CMD_UNLOCK1, addr + 1);
228 writel(CMD_UNLOCK2, addr + 2);
229 writel(CMD_ERASE_SETUP, addr + 1);
wdenk8bde7f72003-06-27 21:31:46 +0000230
wdenk7a8e9bed2003-05-31 18:35:21 +0000231 writel(CMD_UNLOCK1, addr + 1);
232 writel(CMD_UNLOCK2, addr + 2);
233 writel(CMD_ERASE_CONFIRM, addr);
234
wdenk8bde7f72003-06-27 21:31:46 +0000235
wdenk7a8e9bed2003-05-31 18:35:21 +0000236 /* wait until flash is ready */
237 chip1 = chip2 = 0;
wdenk8bde7f72003-06-27 21:31:46 +0000238
wdenk7a8e9bed2003-05-31 18:35:21 +0000239 do {
240 result = readl(addr);
wdenk8bde7f72003-06-27 21:31:46 +0000241
wdenk7a8e9bed2003-05-31 18:35:21 +0000242 /* check timeout */
243 if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
244 writel(CMD_READ_ARRAY, addr + 1);
245 chip1 = TMO;
246 break;
247 }
wdenk8bde7f72003-06-27 21:31:46 +0000248
wdenk7a8e9bed2003-05-31 18:35:21 +0000249 if (!chip1 && (result & 0xFFFF) & BIT_ERASE_DONE) {
250 chip1 = READY;
251 }
wdenk8bde7f72003-06-27 21:31:46 +0000252
wdenk7a8e9bed2003-05-31 18:35:21 +0000253 if (!chip1 && (result & 0xFFFF) & BIT_PROGRAM_ERROR) {
254 chip1 = ERR;
255 }
wdenk8bde7f72003-06-27 21:31:46 +0000256
wdenk7a8e9bed2003-05-31 18:35:21 +0000257 if (!chip2 && (result >> 16) & BIT_ERASE_DONE) {
258 chip2 = READY;
259 }
wdenk8bde7f72003-06-27 21:31:46 +0000260
wdenk7a8e9bed2003-05-31 18:35:21 +0000261 if (!chip2 && (result >> 16) & BIT_PROGRAM_ERROR) {
262 chip2 = ERR;
263 }
wdenk8bde7f72003-06-27 21:31:46 +0000264
wdenk7a8e9bed2003-05-31 18:35:21 +0000265 } while (!chip1 || !chip2);
wdenk8bde7f72003-06-27 21:31:46 +0000266
wdenk7a8e9bed2003-05-31 18:35:21 +0000267 writel(CMD_READ_ARRAY, addr + 1);
wdenk8bde7f72003-06-27 21:31:46 +0000268
wdenk7a8e9bed2003-05-31 18:35:21 +0000269 if (chip1 == ERR || chip2 == ERR) {
270 rc = ERR_PROG_ERROR;
271 goto outahere;
272 }
wdenk8bde7f72003-06-27 21:31:46 +0000273
wdenk7a8e9bed2003-05-31 18:35:21 +0000274 if (chip1 == TMO) {
275 rc = ERR_TIMOUT;
276 goto outahere;
277 }
wdenk8bde7f72003-06-27 21:31:46 +0000278
wdenk7a8e9bed2003-05-31 18:35:21 +0000279 printf("ok.\n");
280 } else { /* it was protected */
wdenk8bde7f72003-06-27 21:31:46 +0000281
wdenk7a8e9bed2003-05-31 18:35:21 +0000282 printf("protected!\n");
283 }
284 }
wdenk8bde7f72003-06-27 21:31:46 +0000285
wdenk7a8e9bed2003-05-31 18:35:21 +0000286 if (ctrlc()) {
287 printf("User Interrupt!\n");
288 }
289
290outahere:
291 /* allow flash to settle - wait 10 ms */
292 udelay(10000);
wdenk8bde7f72003-06-27 21:31:46 +0000293
wdenk7a8e9bed2003-05-31 18:35:21 +0000294 if (iflag) {
295 enable_interrupts();
296 }
wdenk8bde7f72003-06-27 21:31:46 +0000297
wdenk7a8e9bed2003-05-31 18:35:21 +0000298 return rc;
299}
300
301/*-----------------------------------------------------------------------
302 * Copy memory to flash
303 */
304
305volatile static int write_word(flash_info_t *info, ulong dest, ulong data)
306{
307 ulong addr = dest;
308 ulong result;
309 int rc = ERR_OK;
310 int iflag;
311 int chip1, chip2;
wdenk8bde7f72003-06-27 21:31:46 +0000312
wdenk7a8e9bed2003-05-31 18:35:21 +0000313 /*
314 * Check if Flash is (sufficiently) erased
315 */
316 result = readl(addr);
317 if ((result & data) != data) {
318 return ERR_NOT_ERASED;
319 }
wdenk8bde7f72003-06-27 21:31:46 +0000320
wdenk7a8e9bed2003-05-31 18:35:21 +0000321 /*
322 * Disable interrupts which might cause a timeout
323 * here. Remember that our exception vectors are
324 * at address 0 in the flash, and we don't want a
325 * (ticker) exception to happen while the flash
326 * chip is in programming mode.
327 */
328 iflag = disable_interrupts();
329
330 writel(CMD_UNLOCK1, addr + 1);
331 writel(CMD_UNLOCK2, addr + 2);
332 writel(CMD_UNLOCK_BYPASS, addr + 1);
333 writel(addr, CMD_PROGRAM);
334 writel(addr, data);
wdenk8bde7f72003-06-27 21:31:46 +0000335
wdenk7a8e9bed2003-05-31 18:35:21 +0000336 /* arm simple, non interrupt dependent timer */
337 reset_timer();
wdenk8bde7f72003-06-27 21:31:46 +0000338
wdenk7a8e9bed2003-05-31 18:35:21 +0000339 /* wait until flash is ready */
340 chip1 = chip2 = 0;
341 do {
342 result = readl(addr);
wdenk8bde7f72003-06-27 21:31:46 +0000343
wdenk7a8e9bed2003-05-31 18:35:21 +0000344 /* check timeout */
345 if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
346 chip1 = ERR | TMO;
347 break;
348 }
wdenk8bde7f72003-06-27 21:31:46 +0000349
wdenk7a8e9bed2003-05-31 18:35:21 +0000350 if (!chip1 && ((result & 0x80) == (data & 0x80))) {
351 chip1 = READY;
352 }
wdenk8bde7f72003-06-27 21:31:46 +0000353
wdenk7a8e9bed2003-05-31 18:35:21 +0000354 if (!chip1 && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) {
355 result = readl(addr);
wdenk8bde7f72003-06-27 21:31:46 +0000356
wdenk7a8e9bed2003-05-31 18:35:21 +0000357 if ((result & 0x80) == (data & 0x80)) {
358 chip1 = READY;
359 } else {
360 chip1 = ERR;
361 }
362 }
wdenk8bde7f72003-06-27 21:31:46 +0000363
wdenk7a8e9bed2003-05-31 18:35:21 +0000364 if (!chip2 && ((result & (0x80 << 16)) == (data & (0x80 << 16)))) {
365 chip2 = READY;
366 }
wdenk8bde7f72003-06-27 21:31:46 +0000367
wdenk7a8e9bed2003-05-31 18:35:21 +0000368 if (!chip2 && ((result >> 16) & BIT_PROGRAM_ERROR)) {
369 result = readl(addr);
wdenk8bde7f72003-06-27 21:31:46 +0000370
wdenk7a8e9bed2003-05-31 18:35:21 +0000371 if ((result & (0x80 << 16)) == (data & (0x80 << 16))) {
372 chip2 = READY;
373 } else {
374 chip2 = ERR;
375 }
376 }
wdenk8bde7f72003-06-27 21:31:46 +0000377
wdenk7a8e9bed2003-05-31 18:35:21 +0000378 } while (!chip1 || !chip2);
wdenk8bde7f72003-06-27 21:31:46 +0000379
wdenk7a8e9bed2003-05-31 18:35:21 +0000380 writel(CMD_READ_ARRAY, addr);
wdenk8bde7f72003-06-27 21:31:46 +0000381
wdenk7a8e9bed2003-05-31 18:35:21 +0000382 if (chip1 == ERR || chip2 == ERR || readl(addr) != data) {
383 rc = ERR_PROG_ERROR;
384 }
wdenk8bde7f72003-06-27 21:31:46 +0000385
wdenk7a8e9bed2003-05-31 18:35:21 +0000386 if (iflag) {
387 enable_interrupts();
388 }
wdenk8bde7f72003-06-27 21:31:46 +0000389
wdenk7a8e9bed2003-05-31 18:35:21 +0000390 return rc;
391}
392
393/*-----------------------------------------------------------------------
394 * Copy memory to flash.
395 */
396
397int write_buff(flash_info_t *info, uchar *src, ulong addr, ulong cnt)
398{
399 ulong cp, wp, data;
400 int l;
401 int i, rc;
wdenk8bde7f72003-06-27 21:31:46 +0000402
wdenk7a8e9bed2003-05-31 18:35:21 +0000403 wp = (addr & ~3); /* get lower word aligned address */
wdenk8bde7f72003-06-27 21:31:46 +0000404
wdenk7a8e9bed2003-05-31 18:35:21 +0000405 /*
406 * handle unaligned start bytes
407 */
408 if ((l = addr - wp) != 0) {
409 data = 0;
410 for (i=0, cp=wp; i<l; ++i, ++cp) {
411 data = (data >> 8) | (*(uchar *)cp << 24);
412 }
413 for (; i<4 && cnt>0; ++i) {
414 data = (data >> 8) | (*src++ << 24);
415 --cnt;
416 ++cp;
417 }
418 for (; cnt==0 && i<4; ++i, ++cp) {
419 data = (data >> 8) | (*(uchar *)cp << 24);
420 }
wdenk8bde7f72003-06-27 21:31:46 +0000421
wdenk7a8e9bed2003-05-31 18:35:21 +0000422 if ((rc = write_word(info, wp, data)) != 0) {
423 return rc;
424 }
425 wp += 4;
426 }
wdenk8bde7f72003-06-27 21:31:46 +0000427
wdenk7a8e9bed2003-05-31 18:35:21 +0000428 /*
429 * handle word aligned part
430 */
431 while (cnt >= 4) {
432 data = *((vu_long*)src);
433 if ((rc = write_word(info, wp, data)) != 0) {
434 return rc;
435 }
436 src += 4;
437 wp += 4;
438 cnt -= 4;
439 }
wdenk8bde7f72003-06-27 21:31:46 +0000440
wdenk7a8e9bed2003-05-31 18:35:21 +0000441 if (cnt == 0) {
442 return ERR_OK;
443 }
wdenk8bde7f72003-06-27 21:31:46 +0000444
wdenk7a8e9bed2003-05-31 18:35:21 +0000445 /*
446 * handle unaligned tail bytes
447 */
448 data = 0;
449 for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
450 data = (data >> 8) | (*src++ << 24);
451 --cnt;
452 }
453 for (; i<4; ++i, ++cp) {
454 data = (data >> 8) | (*(uchar *)cp << 24);
455 }
wdenk8bde7f72003-06-27 21:31:46 +0000456
wdenk7a8e9bed2003-05-31 18:35:21 +0000457 return write_word(info, wp, data);
458}