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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glassa8cb4fb2015-08-30 16:55:37 -06002/*
3 * Copyright (c) 2013 Google, Inc
Simon Glassa8cb4fb2015-08-30 16:55:37 -06004 */
5
6#include <common.h>
7#include <clk.h>
8#include <dm.h>
Simon Glassbfeb4432016-07-04 11:58:27 -06009#include <dt-structs.h>
Simon Glassa8cb4fb2015-08-30 16:55:37 -060010#include <dwmmc.h>
11#include <errno.h>
Simon Glassbfeb4432016-07-04 11:58:27 -060012#include <mapmem.h>
Simon Glasse1efec42016-01-21 19:43:34 -070013#include <pwrseq.h>
Simon Glassa8cb4fb2015-08-30 16:55:37 -060014#include <syscon.h>
Simon Glasse1efec42016-01-21 19:43:34 -070015#include <asm/gpio.h>
Kever Yang15f09a12019-03-28 11:01:23 +080016#include <asm/arch-rockchip/clock.h>
17#include <asm/arch-rockchip/periph.h>
Simon Glassa8cb4fb2015-08-30 16:55:37 -060018#include <linux/err.h>
19
Simon Glassf6e41d12016-05-14 14:03:08 -060020struct rockchip_mmc_plat {
Simon Glassbfeb4432016-07-04 11:58:27 -060021#if CONFIG_IS_ENABLED(OF_PLATDATA)
22 struct dtd_rockchip_rk3288_dw_mshc dtplat;
23#endif
Simon Glassf6e41d12016-05-14 14:03:08 -060024 struct mmc_config cfg;
25 struct mmc mmc;
26};
27
Simon Glassa8cb4fb2015-08-30 16:55:37 -060028struct rockchip_dwmmc_priv {
Stephen Warren135aa952016-06-17 09:44:00 -060029 struct clk clk;
Simon Glassa8cb4fb2015-08-30 16:55:37 -060030 struct dwmci_host host;
Simon Glass6809b042016-07-04 11:58:26 -060031 int fifo_depth;
32 bool fifo_mode;
33 u32 minmax[2];
Simon Glassa8cb4fb2015-08-30 16:55:37 -060034};
35
36static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
37{
38 struct udevice *dev = host->priv;
39 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
40 int ret;
41
Stephen Warren135aa952016-06-17 09:44:00 -060042 ret = clk_set_rate(&priv->clk, freq);
Simon Glassa8cb4fb2015-08-30 16:55:37 -060043 if (ret < 0) {
Kever Yang419b0802017-06-14 16:31:49 +080044 debug("%s: err=%d\n", __func__, ret);
Simon Glassa8cb4fb2015-08-30 16:55:37 -060045 return ret;
46 }
47
48 return freq;
49}
50
51static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
52{
Simon Glassbfeb4432016-07-04 11:58:27 -060053#if !CONFIG_IS_ENABLED(OF_PLATDATA)
Simon Glassa8cb4fb2015-08-30 16:55:37 -060054 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
55 struct dwmci_host *host = &priv->host;
56
57 host->name = dev->name;
Philipp Tomsichbe5f04e2017-09-11 22:04:15 +020058 host->ioaddr = dev_read_addr_ptr(dev);
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020059 host->buswidth = dev_read_u32_default(dev, "bus-width", 4);
Simon Glassa8cb4fb2015-08-30 16:55:37 -060060 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
61 host->priv = dev;
62
huang linace21982015-11-18 09:37:25 +080063 /* use non-removeable as sdcard and emmc as judgement */
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020064 if (dev_read_bool(dev, "non-removable"))
huang lin65793852016-01-08 14:06:49 +080065 host->dev_index = 0;
66 else
huang linace21982015-11-18 09:37:25 +080067 host->dev_index = 1;
Simon Glassa8cb4fb2015-08-30 16:55:37 -060068
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020069 priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
70
Simon Glass6809b042016-07-04 11:58:26 -060071 if (priv->fifo_depth < 0)
72 return -EINVAL;
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020073 priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
Philipp Tomsichff71f9a2017-04-25 09:52:07 +020074
75 /*
76 * 'clock-freq-min-max' is deprecated
77 * (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
78 */
Philipp Tomsichfd1bf8d2017-06-07 18:46:00 +020079 if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
80 int val = dev_read_u32_default(dev, "max-frequency", -EINVAL);
Philipp Tomsichff71f9a2017-04-25 09:52:07 +020081
82 if (val < 0)
83 return val;
84
85 priv->minmax[0] = 400000; /* 400 kHz */
86 priv->minmax[1] = val;
87 } else {
88 debug("%s: 'clock-freq-min-max' property was deprecated.\n",
89 __func__);
90 }
Simon Glassbfeb4432016-07-04 11:58:27 -060091#endif
Simon Glassa8cb4fb2015-08-30 16:55:37 -060092 return 0;
93}
94
95static int rockchip_dwmmc_probe(struct udevice *dev)
96{
Simon Glassf6e41d12016-05-14 14:03:08 -060097 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
Simon Glassa8cb4fb2015-08-30 16:55:37 -060098 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
99 struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
100 struct dwmci_host *host = &priv->host;
Simon Glasse1efec42016-01-21 19:43:34 -0700101 struct udevice *pwr_dev __maybe_unused;
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600102 int ret;
103
Simon Glassbfeb4432016-07-04 11:58:27 -0600104#if CONFIG_IS_ENABLED(OF_PLATDATA)
105 struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat;
106
107 host->name = dev->name;
108 host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
109 host->buswidth = dtplat->bus_width;
110 host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk;
111 host->priv = dev;
112 host->dev_index = 0;
113 priv->fifo_depth = dtplat->fifo_depth;
114 priv->fifo_mode = 0;
Kever Yang80935292017-06-14 16:31:46 +0800115 priv->minmax[0] = 400000; /* 400 kHz */
116 priv->minmax[1] = dtplat->max_frequency;
Simon Glassbfeb4432016-07-04 11:58:27 -0600117
118 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk);
119 if (ret < 0)
120 return ret;
121#else
Kever Yang419b0802017-06-14 16:31:49 +0800122 ret = clk_get_by_index(dev, 0, &priv->clk);
Simon Glass898d6432016-01-21 19:43:38 -0700123 if (ret < 0)
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600124 return ret;
Simon Glassbfeb4432016-07-04 11:58:27 -0600125#endif
huang lin28637242015-11-17 14:20:24 +0800126 host->fifoth_val = MSIZE(0x2) |
Simon Glass6809b042016-07-04 11:58:26 -0600127 RX_WMARK(priv->fifo_depth / 2 - 1) |
128 TX_WMARK(priv->fifo_depth / 2);
huang lin28637242015-11-17 14:20:24 +0800129
Simon Glass6809b042016-07-04 11:58:26 -0600130 host->fifo_mode = priv->fifo_mode;
huang lin28637242015-11-17 14:20:24 +0800131
Simon Glasse1efec42016-01-21 19:43:34 -0700132#ifdef CONFIG_PWRSEQ
133 /* Enable power if needed */
134 ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq",
135 &pwr_dev);
136 if (!ret) {
137 ret = pwrseq_set_power(pwr_dev, true);
138 if (ret)
139 return ret;
140 }
141#endif
Jaehoon Chunge5113c32016-09-23 19:13:16 +0900142 dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]);
Simon Glassf6e41d12016-05-14 14:03:08 -0600143 host->mmc = &plat->mmc;
Simon Glassf6e41d12016-05-14 14:03:08 -0600144 host->mmc->priv = &priv->host;
Simon Glasscffe5d82016-05-01 13:52:34 -0600145 host->mmc->dev = dev;
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600146 upriv->mmc = host->mmc;
147
Simon Glass42b37d82016-06-12 23:30:24 -0600148 return dwmci_probe(dev);
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600149}
150
Simon Glassf6e41d12016-05-14 14:03:08 -0600151static int rockchip_dwmmc_bind(struct udevice *dev)
152{
Simon Glassf6e41d12016-05-14 14:03:08 -0600153 struct rockchip_mmc_plat *plat = dev_get_platdata(dev);
Simon Glassf6e41d12016-05-14 14:03:08 -0600154
Masahiro Yamada24f5aec2016-09-06 22:17:32 +0900155 return dwmci_bind(dev, &plat->mmc, &plat->cfg);
Simon Glassf6e41d12016-05-14 14:03:08 -0600156}
157
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600158static const struct udevice_id rockchip_dwmmc_ids[] = {
Heiko Stuebner26a52f32018-09-21 10:59:46 +0200159 { .compatible = "rockchip,rk2928-dw-mshc" },
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600160 { .compatible = "rockchip,rk3288-dw-mshc" },
161 { }
162};
163
164U_BOOT_DRIVER(rockchip_dwmmc_drv) = {
Simon Glassbfeb4432016-07-04 11:58:27 -0600165 .name = "rockchip_rk3288_dw_mshc",
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600166 .id = UCLASS_MMC,
167 .of_match = rockchip_dwmmc_ids,
168 .ofdata_to_platdata = rockchip_dwmmc_ofdata_to_platdata,
Simon Glass42b37d82016-06-12 23:30:24 -0600169 .ops = &dm_dwmci_ops,
Simon Glassf6e41d12016-05-14 14:03:08 -0600170 .bind = rockchip_dwmmc_bind,
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600171 .probe = rockchip_dwmmc_probe,
172 .priv_auto_alloc_size = sizeof(struct rockchip_dwmmc_priv),
Simon Glassf6e41d12016-05-14 14:03:08 -0600173 .platdata_auto_alloc_size = sizeof(struct rockchip_mmc_plat),
Simon Glassa8cb4fb2015-08-30 16:55:37 -0600174};
Simon Glasse1efec42016-01-21 19:43:34 -0700175
176#ifdef CONFIG_PWRSEQ
177static int rockchip_dwmmc_pwrseq_set_power(struct udevice *dev, bool enable)
178{
179 struct gpio_desc reset;
180 int ret;
181
182 ret = gpio_request_by_name(dev, "reset-gpios", 0, &reset, GPIOD_IS_OUT);
183 if (ret)
184 return ret;
185 dm_gpio_set_value(&reset, 1);
186 udelay(1);
187 dm_gpio_set_value(&reset, 0);
188 udelay(200);
189
190 return 0;
191}
192
193static const struct pwrseq_ops rockchip_dwmmc_pwrseq_ops = {
194 .set_power = rockchip_dwmmc_pwrseq_set_power,
195};
196
197static const struct udevice_id rockchip_dwmmc_pwrseq_ids[] = {
198 { .compatible = "mmc-pwrseq-emmc" },
199 { }
200};
201
202U_BOOT_DRIVER(rockchip_dwmmc_pwrseq_drv) = {
203 .name = "mmc_pwrseq_emmc",
204 .id = UCLASS_PWRSEQ,
205 .of_match = rockchip_dwmmc_pwrseq_ids,
206 .ops = &rockchip_dwmmc_pwrseq_ops,
207};
208#endif