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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
wdenkc6097192002-11-03 00:24:07 +00002/*
3 * (C) Copyright 2002
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenkc6097192002-11-03 00:24:07 +00005 */
6
7#include <fpga.h>
8
9#ifndef _ALTERA_H_
10#define _ALTERA_H_
11
Stefan Roeseff9c4c52016-02-12 13:48:02 +010012/*
13 * For the StratixV FPGA programming via SPI, the following
14 * information is coded in the 32bit cookie:
15 * Bit 31 ... Bit 0
16 * SPI-Bus | SPI-Dev | Config-Pin | Done-Pin
17 */
18#define FPGA_COOKIE(bus, dev, config, done) \
19 (((bus) << 24) | ((dev) << 16) | ((config) << 8) | (done))
20#define COOKIE2SPI_BUS(c) (((c) >> 24) & 0xff)
21#define COOKIE2SPI_DEV(c) (((c) >> 16) & 0xff)
22#define COOKIE2CONFIG(c) (((c) >> 8) & 0xff)
23#define COOKIE2DONE(c) ((c) & 0xff)
24
Marek Vasutd44ef7f2014-09-16 20:48:33 +020025enum altera_iface {
26 /* insert all new types after this */
27 min_altera_iface_type,
28 /* serial data and external clock */
29 passive_serial,
30 /* parallel data */
31 passive_parallel_synchronous,
32 /* parallel data */
33 passive_parallel_asynchronous,
34 /* serial data w/ internal clock (not used) */
35 passive_serial_asynchronous,
36 /* jtag/tap serial (not used ) */
37 altera_jtag_mode,
38 /* fast passive parallel (FPP) */
39 fast_passive_parallel,
40 /* fast passive parallel with security (FPPS) */
41 fast_passive_parallel_security,
Ang, Chee Hong877ec6e2018-12-19 18:35:15 -080042 /* secure device manager (SDM) mailbox */
43 secure_device_manager_mailbox,
Marek Vasutd44ef7f2014-09-16 20:48:33 +020044 /* insert all new types before this */
45 max_altera_iface_type,
46};
wdenkc6097192002-11-03 00:24:07 +000047
Marek Vasutd44ef7f2014-09-16 20:48:33 +020048enum altera_family {
49 /* insert all new types after this */
50 min_altera_type,
51 /* ACEX1K Family */
52 Altera_ACEX1K,
53 /* CYCLONII Family */
54 Altera_CYC2,
55 /* StratixII Family */
56 Altera_StratixII,
Stefan Roeseff9c4c52016-02-12 13:48:02 +010057 /* StratixV Family */
58 Altera_StratixV,
Pavel Machek230fe9b2014-09-08 14:08:45 +020059 /* SoCFPGA Family */
60 Altera_SoCFPGA,
Chee Hong Angd2170162020-08-07 11:50:03 +080061 /* Intel FPGA Family with SDM (Secure Device Manager) Mailbox */
62 Intel_FPGA_SDM_Mailbox,
wdenkc6097192002-11-03 00:24:07 +000063
Marek Vasutd44ef7f2014-09-16 20:48:33 +020064 /* Add new models here */
65
66 /* insert all new types before this */
67 max_altera_type,
68};
69
70typedef struct {
71 /* part type */
72 enum altera_family family;
73 /* interface type */
74 enum altera_iface iface;
75 /* bytes of data part can accept */
76 size_t size;
77 /* interface function table */
78 void *iface_fns;
79 /* base interface address */
80 void *base;
81 /* implementation specific cookie */
82 int cookie;
83} Altera_desc;
wdenkc6097192002-11-03 00:24:07 +000084
wdenk5da627a2003-10-09 20:09:04 +000085/* Generic Altera Functions
86 *********************************************************************/
Wolfgang Denke6a857d2011-07-30 13:33:49 +000087extern int altera_load(Altera_desc *desc, const void *image, size_t size);
88extern int altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
89extern int altera_info(Altera_desc *desc);
wdenkc6097192002-11-03 00:24:07 +000090
wdenk5da627a2003-10-09 20:09:04 +000091/* Board specific implementation specific function types
92 *********************************************************************/
93typedef int (*Altera_pre_fn)( int cookie );
94typedef int (*Altera_config_fn)( int assert_config, int flush, int cookie );
95typedef int (*Altera_status_fn)( int cookie );
96typedef int (*Altera_done_fn)( int cookie );
97typedef int (*Altera_clk_fn)( int assert_clk, int flush, int cookie );
98typedef int (*Altera_data_fn)( int assert_data, int flush, int cookie );
Wolfgang Denke6a857d2011-07-30 13:33:49 +000099typedef int(*Altera_write_fn)(const void *buf, size_t len, int flush, int cookie);
wdenk5da627a2003-10-09 20:09:04 +0000100typedef int (*Altera_abort_fn)( int cookie );
101typedef int (*Altera_post_fn)( int cookie );
102
eran liberty3c735e72008-03-27 00:50:49 +0100103typedef struct {
104 Altera_pre_fn pre;
105 Altera_config_fn config;
106 Altera_status_fn status;
107 Altera_done_fn done;
108 Altera_clk_fn clk;
109 Altera_data_fn data;
Stefan Roeseff9c4c52016-02-12 13:48:02 +0100110 Altera_write_fn write;
eran liberty3c735e72008-03-27 00:50:49 +0100111 Altera_abort_fn abort;
112 Altera_post_fn post;
113} altera_board_specific_func;
114
Pavel Machek230fe9b2014-09-08 14:08:45 +0200115#ifdef CONFIG_FPGA_SOCFPGA
116int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
117#endif
118
Stefan Roeseff9c4c52016-02-12 13:48:02 +0100119#ifdef CONFIG_FPGA_STRATIX_V
120int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
121#endif
122
Chee Hong Angd2170162020-08-07 11:50:03 +0800123#ifdef CONFIG_FPGA_INTEL_SDM_MAILBOX
124int intel_sdm_mb_load(Altera_desc *desc, const void *rbf_data,
125 size_t rbf_size);
Ang, Chee Hongc41e6602018-12-19 18:35:14 -0800126#endif
127
wdenk5da627a2003-10-09 20:09:04 +0000128#endif /* _ALTERA_H_ */