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Bin Meng5dad97e2014-12-17 15:50:48 +08001#
2# Copyright (C) 2014, Simon Glass <sjg@chromium.org>
3# Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4#
5# SPDX-License-Identifier: GPL-2.0+
6#
7
8U-Boot on x86
9=============
10
11This document describes the information about U-Boot running on x86 targets,
12including supported boards, build instructions, todo list, etc.
13
14Status
15------
16U-Boot supports running as a coreboot [1] payload on x86. So far only Link
17(Chromebook Pixel) has been tested, but it should work with minimal adjustments
18on other x86 boards since coreboot deals with most of the low-level details.
19
20U-Boot also supports booting directly from x86 reset vector without coreboot,
Bin Meng67582c02015-02-04 16:26:14 +080021aka raw support or bare support. Currently Link, Intel Crown Bay, Intel
22Minnowboard Max and Intel Galileo support running U-Boot 'bare metal'.
Bin Meng5dad97e2014-12-17 15:50:48 +080023
Simon Glass3a1a18f2015-01-27 22:13:47 -070024As for loading an OS, U-Boot supports directly booting a 32-bit or 64-bit
25Linux kernel as part of a FIT image. It also supports a compressed zImage.
Bin Meng5dad97e2014-12-17 15:50:48 +080026
27Build Instructions
28------------------
29Building U-Boot as a coreboot payload is just like building U-Boot for targets
30on other architectures, like below:
31
32$ make coreboot-x86_defconfig
33$ make all
34
Bin Meng617b8672015-01-06 22:14:24 +080035Note this default configuration will build a U-Boot payload for the Link board.
36To build a coreboot payload against another board, you can change the build
37configuration during the 'make menuconfig' process.
38
39x86 architecture --->
40 ...
41 (chromebook_link) Board configuration file
42 (chromebook_link) Board Device Tree Source (dts) file
43 (0x19200000) Board specific Cache-As-RAM (CAR) address
44 (0x4000) Board specific Cache-As-RAM (CAR) size
45
46Change the 'Board configuration file' and 'Board Device Tree Source (dts) file'
47to point to a new board. You can also change the Cache-As-RAM (CAR) related
48settings here if the default values do not fit your new board.
49
Simon Glass3a1a18f2015-01-27 22:13:47 -070050Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
Bin Meng5dad97e2014-12-17 15:50:48 +080051little bit tricky, as generally it requires several binary blobs which are not
52shipped in the U-Boot source tree. Due to this reason, the u-boot.rom build is
53not turned on by default in the U-Boot source tree. Firstly, you need turn it
Simon Glasseea0f112015-01-27 22:13:32 -070054on by enabling the ROM build:
Bin Meng5dad97e2014-12-17 15:50:48 +080055
Simon Glasseea0f112015-01-27 22:13:32 -070056$ export BUILD_ROM=y
57
58This tells the Makefile to build u-boot.rom as a target.
Bin Meng5dad97e2014-12-17 15:50:48 +080059
60Link-specific instructions:
61
62First, you need the following binary blobs:
63
64* descriptor.bin - Intel flash descriptor
65* me.bin - Intel Management Engine
66* mrc.bin - Memory Reference Code, which sets up SDRAM
67* video ROM - sets up the display
68
69You can get these binary blobs by:
70
71$ git clone http://review.coreboot.org/p/blobs.git
72$ cd blobs
73
74Find the following files:
75
76* ./mainboard/google/link/descriptor.bin
77* ./mainboard/google/link/me.bin
78* ./northbridge/intel/sandybridge/systemagent-ivybridge.bin
79
80The 3rd one should be renamed to mrc.bin.
81As for the video ROM, you can get it here [2].
82Make sure all these binary blobs are put in the board directory.
83
84Now you can build U-Boot and obtain u-boot.rom:
85
86$ make chromebook_link_defconfig
87$ make all
88
89Intel Crown Bay specific instructions:
90
91U-Boot support of Intel Crown Bay board [3] relies on a binary blob called
92Firmware Support Package [4] to perform all the necessary initialization steps
93as documented in the BIOS Writer Guide, including initialization of the CPU,
94memory controller, chipset and certain bus interfaces.
95
96Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T,
97install it on your host and locate the FSP binary blob. Note this platform
98also requires a Chipset Micro Code (CMC) state machine binary to be present in
99the SPI flash where u-boot.rom resides, and this CMC binary blob can be found
100in this FSP package too.
101
102* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd
103* ./Microcode/C0_22211.BIN
104
105Rename the first one to fsp.bin and second one to cmc.bin and put them in the
106board directory.
107
Bin Meng83d97122015-03-05 11:21:03 +0800108Note the FSP release version 001 has a bug which could cause random endless
109loop during the FspInit call. This bug was published by Intel although Intel
110did not describe any details. We need manually apply the patch to the FSP
111binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP
112binary, change the following five bytes values from orginally E8 42 FF FF FF
113to B8 00 80 0B 00.
114
Bin Meng617b8672015-01-06 22:14:24 +0800115Now you can build U-Boot and obtain u-boot.rom
Bin Meng5dad97e2014-12-17 15:50:48 +0800116
117$ make crownbay_defconfig
118$ make all
119
Simon Glass3a1a18f2015-01-27 22:13:47 -0700120Intel Minnowboard Max instructions:
121
122This uses as FSP as with Crown Bay, except it is for the Atom E3800 series.
123Download this and get the .fd file (BAYTRAIL_FSP_GOLD_003_16-SEP-2014.fd at
124the time of writing). Put it in the board directory:
125board/intel/minnowmax/fsp.bin
126
127Obtain the VGA RAM (Vga.dat at the time of writing) and put it into the same
128directory: board/intel/minnowmax/vga.bin
129
130You still need two more binary blobs. These come from the sample SPI image
131provided in the FSP (SPI.bin at the time of writing).
132
133Use ifdtool in the U-Boot tools directory to extract the images from that
134file, for example:
135
136 $ ./tools/ifdtool -x BayleyBay/SPI.bin
137 $ cp flashregion_2_intel_me.bin board/intel/minnowmax/me.bin
138 $ cp flashregion_0_flashdescriptor.bin board/intel/minnowmax/descriptor.bin
139
140Now you can build U-Boot and obtain u-boot.rom
141
142$ make minnowmax_defconfig
143$ make all
144
Bin Meng67582c02015-02-04 16:26:14 +0800145Intel Galileo instructions:
146
147Only one binary blob is needed for Remote Management Unit (RMU) within Intel
148Quark SoC. Not like FSP, U-Boot does not call into the binary. The binary is
149needed by the Quark SoC itself.
150
151You can get the binary blob from Quark Board Support Package from Intel website:
152
153* ./QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
154
155Rename the file and put it to the board directory by:
156
157 $ cp RMU.bin board/intel/galileo/rmu.bin
158
159Now you can build U-Boot and obtain u-boot.rom
160
161$ make galileo_defconfig
162$ make all
Simon Glass3a1a18f2015-01-27 22:13:47 -0700163
Bin Meng617b8672015-01-06 22:14:24 +0800164Test with coreboot
165------------------
166For testing U-Boot as the coreboot payload, there are things that need be paid
167attention to. coreboot supports loading an ELF executable and a 32-bit plain
168binary, as well as other supported payloads. With the default configuration,
169U-Boot is set up to use a separate Device Tree Blob (dtb). As of today, the
170generated u-boot-dtb.bin needs to be packaged by the cbfstool utility (a tool
171provided by coreboot) manually as coreboot's 'make menuconfig' does not provide
172this capability yet. The command is as follows:
173
174# in the coreboot root directory
175$ ./build/util/cbfstool/cbfstool build/coreboot.rom add-flat-binary \
176 -f u-boot-dtb.bin -n fallback/payload -c lzma -l 0x1110000 -e 0x1110015
177
178Make sure 0x1110000 matches CONFIG_SYS_TEXT_BASE and 0x1110015 matches the
179symbol address of _start (in arch/x86/cpu/start.S).
180
181If you want to use ELF as the coreboot payload, change U-Boot configuration to
Simon Glasseea0f112015-01-27 22:13:32 -0700182use CONFIG_OF_EMBED instead of CONFIG_OF_SEPARATE.
Bin Meng617b8672015-01-06 22:14:24 +0800183
Simon Glass3a1a18f2015-01-27 22:13:47 -0700184To enable video you must enable these options in coreboot:
185
186 - Set framebuffer graphics resolution (1280x1024 32k-color (1:5:5))
187 - Keep VESA framebuffer
188
189At present it seems that for Minnowboard Max, coreboot does not pass through
190the video information correctly (it always says the resolution is 0x0). This
191works correctly for link though.
192
193
Bin Meng5dad97e2014-12-17 15:50:48 +0800194CPU Microcode
195-------------
Simon Glasseea0f112015-01-27 22:13:32 -0700196Modern CPUs usually require a special bit stream called microcode [5] to be
Bin Meng5dad97e2014-12-17 15:50:48 +0800197loaded on the processor after power up in order to function properly. U-Boot
198has already integrated these as hex dumps in the source tree.
199
200Driver Model
201------------
202x86 has been converted to use driver model for serial and GPIO.
203
204Device Tree
205-----------
206x86 uses device tree to configure the board thus requires CONFIG_OF_CONTROL to
Bin Meng617b8672015-01-06 22:14:24 +0800207be turned on. Not every device on the board is configured via device tree, but
Bin Meng5dad97e2014-12-17 15:50:48 +0800208more and more devices will be added as time goes by. Check out the directory
209arch/x86/dts/ for these device tree source files.
210
Simon Glasscb3b2e62015-01-01 16:18:15 -0700211Useful Commands
212---------------
213
214In keeping with the U-Boot philosophy of providing functions to check and
215adjust internal settings, there are several x86-specific commands that may be
216useful:
217
218hob - Display information about Firmware Support Package (FSP) Hand-off
219 Block. This is only available on platforms which use FSP, mostly
220 Atom.
221iod - Display I/O memory
222iow - Write I/O memory
223mtrr - List and set the Memory Type Range Registers (MTRR). These are used to
224 tell the CPU whether memory is cacheable and if so the cache write
225 mode to use. U-Boot sets up some reasonable values but you can
226 adjust then with this command.
227
Simon Glass00bdd952015-01-27 22:13:46 -0700228Development Flow
229----------------
Simon Glass00bdd952015-01-27 22:13:46 -0700230These notes are for those who want to port U-Boot to a new x86 platform.
231
232Since x86 CPUs boot from SPI flash, a SPI flash emulator is a good investment.
233The Dediprog em100 can be used on Linux. The em100 tool is available here:
234
235 http://review.coreboot.org/p/em100.git
236
237On Minnowboard Max the following command line can be used:
238
239 sudo em100 -s -p LOW -d u-boot.rom -c W25Q64DW -r
240
241A suitable clip for connecting over the SPI flash chip is here:
242
243 http://www.dediprog.com/pd/programmer-accessories/EM-TC-8
244
245This allows you to override the SPI flash contents for development purposes.
246Typically you can write to the em100 in around 1200ms, considerably faster
247than programming the real flash device each time. The only important
248limitation of the em100 is that it only supports SPI bus speeds up to 20MHz.
249This means that images must be set to boot with that speed. This is an
250Intel-specific feature - e.g. tools/ifttool has an option to set the SPI
251speed in the SPI descriptor region.
252
253If your chip/board uses an Intel Firmware Support Package (FSP) it is fairly
254easy to fit it in. You can follow the Minnowboard Max implementation, for
255example. Hopefully you will just need to create new files similar to those
256in arch/x86/cpu/baytrail which provide Bay Trail support.
257
258If you are not using an FSP you have more freedom and more responsibility.
259The ivybridge support works this way, although it still uses a ROM for
260graphics and still has binary blobs containing Intel code. You should aim to
261support all important peripherals on your platform including video and storage.
262Use the device tree for configuration where possible.
263
264For the microcode you can create a suitable device tree file using the
265microcode tool:
266
267 ./tools/microcode-tool -d microcode.dat create <model>
268
269or if you only have header files and not the full Intel microcode.dat database:
270
271 ./tools/microcode-tool -H BAY_TRAIL_FSP_KIT/Microcode/M0130673322.h \
272 -H BAY_TRAIL_FSP_KIT/Microcode/M0130679901.h \
273 create all
274
275These are written to arch/x86/dts/microcode/ by default.
276
277Note that it is possible to just add the micrcode for your CPU if you know its
278model. U-Boot prints this information when it starts
279
280 CPU: x86_64, vendor Intel, device 30673h
281
282so here we can use the M0130673322 file.
283
284If you platform can display POST codes on two little 7-segment displays on
285the board, then you can use post_code() calls from C or assembler to monitor
286boot progress. This can be good for debugging.
287
288If not, you can try to get serial working as early as possible. The early
289debug serial port may be useful here. See setup_early_uart() for an example.
290
Bin Meng5dad97e2014-12-17 15:50:48 +0800291TODO List
292---------
Bin Meng5dad97e2014-12-17 15:50:48 +0800293- Audio
294- Chrome OS verified boot
295- SMI and ACPI support, to provide platform info and facilities to Linux
296
297References
298----------
299[1] http://www.coreboot.org
300[2] http://www.coreboot.org/~stepan/pci8086,0166.rom
301[3] http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html
302[4] http://www.intel.com/fsp
303[5] http://en.wikipedia.org/wiki/Microcode