blob: 4099a74a4af2cf0b86a4664c6d367a176ba90861 [file] [log] [blame]
Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Sun34e026f2014-03-27 17:54:47 -07002 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05003 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#ifndef FSL_DDR_MAIN_H
10#define FSL_DDR_MAIN_H
11
York Sun34e026f2014-03-27 17:54:47 -070012#include <fsl_ddrc_version.h>
York Sun5614e712013-09-30 09:22:09 -070013#include <fsl_ddr_sdram.h>
14#include <fsl_ddr_dimm_params.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050015
York Sun5614e712013-09-30 09:22:09 -070016#include <common_timing_params.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050017
York Sun1d71efb2014-08-01 15:51:00 -070018#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
19/* All controllers are for main memory */
20#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS
21#endif
22
York Sun4e5b1bd2014-02-10 13:59:42 -080023#ifdef CONFIG_SYS_FSL_DDR_LE
24#define ddr_in32(a) in_le32(a)
25#define ddr_out32(a, v) out_le32(a, v)
York Sundda3b612014-12-08 15:30:55 -080026#define ddr_setbits32(a, v) setbits_le32(a, v)
27#define ddr_clrbits32(a, v) clrbits_le32(a, v)
28#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
York Sun4e5b1bd2014-02-10 13:59:42 -080029#else
30#define ddr_in32(a) in_be32(a)
31#define ddr_out32(a, v) out_be32(a, v)
York Sundda3b612014-12-08 15:30:55 -080032#define ddr_setbits32(a, v) setbits_be32(a, v)
33#define ddr_clrbits32(a, v) clrbits_be32(a, v)
34#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
York Sun4e5b1bd2014-02-10 13:59:42 -080035#endif
36
York Sun66869f92015-03-19 09:30:26 -070037u32 fsl_ddr_get_version(unsigned int ctrl_num);
York Sun34e026f2014-03-27 17:54:47 -070038
York Sun1b3e3c42011-06-07 09:42:16 +080039#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050040/*
41 * Bind the main DDR setup driver's generic names
42 * to this specific DDR technology.
43 */
44static __inline__ int
York Sun03e664d2015-01-06 13:18:50 -080045compute_dimm_parameters(const unsigned int ctrl_num,
46 const generic_spd_eeprom_t *spd,
Kumar Gala58e5e9a2008-08-26 15:01:29 -050047 dimm_params_t *pdimm,
48 unsigned int dimm_number)
49{
York Sun03e664d2015-01-06 13:18:50 -080050 return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050051}
York Sun1b3e3c42011-06-07 09:42:16 +080052#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -050053
54/*
55 * Data Structures
56 *
57 * All data structures have to be on the stack
58 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020059#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS
60#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
Kumar Gala58e5e9a2008-08-26 15:01:29 -050061
62typedef struct {
63 generic_spd_eeprom_t
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
Kumar Gala58e5e9a2008-08-26 15:01:29 -050065 struct dimm_params_s
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066 dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
67 memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
68 common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
69 fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
York Sun1d71efb2014-08-01 15:51:00 -070070 unsigned int first_ctrl;
71 unsigned int num_ctrls;
72 unsigned long long mem_base;
73 unsigned int dimm_slots_per_ctrl;
74 int (*board_need_mem_reset)(void);
75 void (*board_mem_reset)(void);
76 void (*board_mem_de_reset)(void);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050077} fsl_ddr_info_t;
78
79/* Compute steps */
80#define STEP_GET_SPD (1 << 0)
81#define STEP_COMPUTE_DIMM_PARMS (1 << 1)
82#define STEP_COMPUTE_COMMON_PARMS (1 << 2)
83#define STEP_GATHER_OPTS (1 << 3)
84#define STEP_ASSIGN_ADDRESSES (1 << 4)
85#define STEP_COMPUTE_REGS (1 << 5)
86#define STEP_PROGRAM_REGS (1 << 6)
87#define STEP_ALL 0xFFF
88
York Sun6f5e1dc2011-09-16 13:21:35 -070089unsigned long long
Haiying Wangfc0c2b62010-12-01 10:35:31 -050090fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
91 unsigned int size_only);
York Sun6f5e1dc2011-09-16 13:21:35 -070092const char *step_to_string(unsigned int step);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050093
York Sun03e664d2015-01-06 13:18:50 -080094unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
95 const memctl_options_t *popts,
Kumar Gala58e5e9a2008-08-26 15:01:29 -050096 fsl_ddr_cfg_regs_t *ddr,
97 const common_timing_params_t *common_dimm,
98 const dimm_params_t *dimm_parameters,
Haiying Wangfc0c2b62010-12-01 10:35:31 -050099 unsigned int dbw_capacity_adjust,
100 unsigned int size_only);
York Sun6f5e1dc2011-09-16 13:21:35 -0700101unsigned int compute_lowest_common_dimm_parameters(
York Sun03e664d2015-01-06 13:18:50 -0800102 const unsigned int ctrl_num,
York Sun6f5e1dc2011-09-16 13:21:35 -0700103 const dimm_params_t *dimm_params,
104 common_timing_params_t *outpdimm,
105 unsigned int number_of_dimms);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530106unsigned int populate_memctl_options(int all_dimms_registered,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500107 memctl_options_t *popts,
Haiying Wangdfb49102008-10-03 12:36:55 -0400108 dimm_params_t *pdimm,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500109 unsigned int ctrl_num);
York Sun6f5e1dc2011-09-16 13:21:35 -0700110void check_interleaving_options(fsl_ddr_info_t *pinfo);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500111
York Sun03e664d2015-01-06 13:18:50 -0800112unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
113unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
114unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
York Sun6f5e1dc2011-09-16 13:21:35 -0700115void fsl_ddr_set_lawbar(
116 const common_timing_params_t *memctl_common_params,
117 unsigned int memctl_interleaved,
118 unsigned int ctrl_num);
York Sune32d59a2015-01-06 13:18:55 -0800119void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
120 unsigned int last_ctrl);
York Sun6f5e1dc2011-09-16 13:21:35 -0700121
James Yange8ba6c52013-01-07 14:01:03 +0000122int fsl_ddr_interactive_env_var_exists(void);
123unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
York Sun6f5e1dc2011-09-16 13:21:35 -0700124void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
York Sun1d71efb2014-08-01 15:51:00 -0700125 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
York Sun6f5e1dc2011-09-16 13:21:35 -0700126
127int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
128unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
York Sun4e5b1bd2014-02-10 13:59:42 -0800129void board_add_ram_info(int use_default);
York Sun6f5e1dc2011-09-16 13:21:35 -0700130
131/* processor specific function */
132void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
York Sunc63e1372013-06-25 11:37:48 -0700133 unsigned int ctrl_num, int step);
York Sun1b3e3c42011-06-07 09:42:16 +0800134
135/* board specific function */
136int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
137 unsigned int controller_number,
138 unsigned int dimm_number);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500139#endif