blob: 08815994fe5d21d0effd00394cea05ce6698508c [file] [log] [blame]
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +02001/*
2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +02005 */
6
7#include <common.h>
Haavard Skinnemoend255bb02008-05-16 11:10:31 +02008#include <malloc.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +02009#include <spi.h>
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +010010#include <asm/errno.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020011#include <asm/io.h>
Stefano Babicd8e0ca82011-08-21 10:45:44 +020012#include <asm/gpio.h>
Stefano Babic86271112011-03-14 15:43:56 +010013#include <asm/arch/imx-regs.h>
14#include <asm/arch/clock.h>
Eric Nelson3acb0112014-09-30 15:40:03 -070015#include <asm/imx-common/spi.h>
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020016
17#ifdef CONFIG_MX27
18/* i.MX27 has a completely wrong register layout and register definitions in the
19 * datasheet, the correct one is in the Freescale's Linux driver */
20
Helmut Raiger61a58a12011-06-15 01:45:45 +000021#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020022"See linux mxc_spi driver from Freescale for details."
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020023#endif
24
Eric Nelson08c61a52012-01-31 07:52:03 +000025static unsigned long spi_bases[] = {
26 MXC_SPI_BASE_ADDRESSES
27};
28
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +030029__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
30{
31 return -1;
32}
33
Stefano Babicc4ea1422010-07-06 17:05:06 +020034#define OUT MXC_GPIO_DIRECTION_OUT
35
Stefano Babicac87c172011-01-19 22:46:33 +000036#define reg_read readl
37#define reg_write(a, v) writel(v, a)
38
Heiko Schocherf659b572014-07-14 10:22:11 +020039#if !defined(CONFIG_SYS_SPI_MXC_WAIT)
40#define CONFIG_SYS_SPI_MXC_WAIT (CONFIG_SYS_HZ/100) /* 10 ms */
41#endif
42
Haavard Skinnemoend255bb02008-05-16 11:10:31 +020043struct mxc_spi_slave {
44 struct spi_slave slave;
45 unsigned long base;
46 u32 ctrl_reg;
Eric Nelson08c61a52012-01-31 07:52:03 +000047#if defined(MXC_ECSPI)
Stefano Babicd205ddc2010-04-04 22:43:38 +020048 u32 cfg_reg;
49#endif
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +010050 int gpio;
Stefano Babicc4ea1422010-07-06 17:05:06 +020051 int ss_pol;
Markus Niebel027a9a02014-10-23 16:09:39 +020052 unsigned int max_hz;
53 unsigned int mode;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020054};
Haavard Skinnemoend255bb02008-05-16 11:10:31 +020055
56static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
57{
58 return container_of(slave, struct mxc_spi_slave, slave);
59}
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +020060
Stefano Babicd205ddc2010-04-04 22:43:38 +020061void spi_cs_activate(struct spi_slave *slave)
62{
63 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
64 if (mxcs->gpio > 0)
Stefano Babicd8e0ca82011-08-21 10:45:44 +020065 gpio_set_value(mxcs->gpio, mxcs->ss_pol);
Stefano Babicd205ddc2010-04-04 22:43:38 +020066}
67
68void spi_cs_deactivate(struct spi_slave *slave)
69{
70 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
71 if (mxcs->gpio > 0)
Stefano Babicd8e0ca82011-08-21 10:45:44 +020072 gpio_set_value(mxcs->gpio,
Stefano Babicc4ea1422010-07-06 17:05:06 +020073 !(mxcs->ss_pol));
Stefano Babicd205ddc2010-04-04 22:43:38 +020074}
75
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +000076u32 get_cspi_div(u32 div)
77{
78 int i;
79
80 for (i = 0; i < 8; i++) {
81 if (div <= (4 << i))
82 return i;
83 }
84 return i;
85}
86
Eric Nelson08c61a52012-01-31 07:52:03 +000087#ifdef MXC_CSPI
Markus Niebel027a9a02014-10-23 16:09:39 +020088static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babicc9d59c72011-01-19 22:46:30 +000089{
90 unsigned int ctrl_reg;
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +000091 u32 clk_src;
92 u32 div;
Markus Niebel027a9a02014-10-23 16:09:39 +020093 unsigned int max_hz = mxcs->max_hz;
94 unsigned int mode = mxcs->mode;
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +000095
96 clk_src = mxc_get_clock(MXC_CSPI_CLK);
97
Benoît Thébaudeaucd200402012-08-10 08:51:50 +000098 div = DIV_ROUND_UP(clk_src, max_hz);
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +000099 div = get_cspi_div(div);
100
101 debug("clk %d Hz, div %d, real clk %d Hz\n",
102 max_hz, div, clk_src / (4 << div));
Stefano Babicc9d59c72011-01-19 22:46:30 +0000103
104 ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
105 MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
Anatolij Gustschinafaa9f62011-01-19 22:46:32 +0000106 MXC_CSPICTRL_DATARATE(div) |
Stefano Babicc9d59c72011-01-19 22:46:30 +0000107 MXC_CSPICTRL_EN |
108#ifdef CONFIG_MX35
109 MXC_CSPICTRL_SSCTL |
110#endif
111 MXC_CSPICTRL_MODE;
112
113 if (mode & SPI_CPHA)
114 ctrl_reg |= MXC_CSPICTRL_PHA;
115 if (mode & SPI_CPOL)
116 ctrl_reg |= MXC_CSPICTRL_POL;
117 if (mode & SPI_CS_HIGH)
118 ctrl_reg |= MXC_CSPICTRL_SSPOL;
119 mxcs->ctrl_reg = ctrl_reg;
120
121 return 0;
122}
123#endif
124
Eric Nelson08c61a52012-01-31 07:52:03 +0000125#ifdef MXC_ECSPI
Markus Niebel027a9a02014-10-23 16:09:39 +0200126static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
Stefano Babicd205ddc2010-04-04 22:43:38 +0200127{
128 u32 clk_src = mxc_get_clock(MXC_CSPI_CLK);
Dirk Behme9a309032013-05-11 07:25:54 +0200129 s32 reg_ctrl, reg_config;
Markus Niebel5d584cc2014-02-17 17:33:17 +0100130 u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0;
131 u32 pre_div = 0, post_div = 0;
Stefano Babicac87c172011-01-19 22:46:33 +0000132 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Markus Niebel027a9a02014-10-23 16:09:39 +0200133 unsigned int max_hz = mxcs->max_hz;
134 unsigned int mode = mxcs->mode;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200135
Fabio Estevam0f1411b2013-04-09 13:06:25 +0000136 /*
137 * Reset SPI and set all CSs to master mode, if toggling
138 * between slave and master mode we might see a glitch
139 * on the clock line
140 */
141 reg_ctrl = MXC_CSPICTRL_MODE_MASK;
142 reg_write(&regs->ctrl, reg_ctrl);
143 reg_ctrl |= MXC_CSPICTRL_EN;
144 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200145
Stefano Babicd205ddc2010-04-04 22:43:38 +0200146 if (clk_src > max_hz) {
Dirk Behme9a309032013-05-11 07:25:54 +0200147 pre_div = (clk_src - 1) / max_hz;
148 /* fls(1) = 1, fls(0x80000000) = 32, fls(16) = 5 */
149 post_div = fls(pre_div);
150 if (post_div > 4) {
151 post_div -= 4;
152 if (post_div >= 16) {
Stefano Babicd205ddc2010-04-04 22:43:38 +0200153 printf("Error: no divider for the freq: %d\n",
154 max_hz);
155 return -1;
156 }
Dirk Behme9a309032013-05-11 07:25:54 +0200157 pre_div >>= post_div;
158 } else {
159 post_div = 0;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200160 }
161 }
162
163 debug("pre_div = %d, post_div=%d\n", pre_div, post_div);
164 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_SELCHAN(3)) |
165 MXC_CSPICTRL_SELCHAN(cs);
166 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_PREDIV(0x0F)) |
167 MXC_CSPICTRL_PREDIV(pre_div);
168 reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) |
169 MXC_CSPICTRL_POSTDIV(post_div);
170
Stefano Babicd205ddc2010-04-04 22:43:38 +0200171 if (mode & SPI_CS_HIGH)
172 ss_pol = 1;
173
Markus Niebel5d584cc2014-02-17 17:33:17 +0100174 if (mode & SPI_CPOL) {
Stefano Babicd205ddc2010-04-04 22:43:38 +0200175 sclkpol = 1;
Markus Niebel5d584cc2014-02-17 17:33:17 +0100176 sclkctl = 1;
177 }
Stefano Babicd205ddc2010-04-04 22:43:38 +0200178
179 if (mode & SPI_CPHA)
180 sclkpha = 1;
181
Stefano Babicac87c172011-01-19 22:46:33 +0000182 reg_config = reg_read(&regs->cfg);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200183
184 /*
185 * Configuration register setup
Stefano Babicc9d59c72011-01-19 22:46:30 +0000186 * The MX51 supports different setup for each SS
Stefano Babicd205ddc2010-04-04 22:43:38 +0200187 */
188 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_SSPOL))) |
189 (ss_pol << (cs + MXC_CSPICON_SSPOL));
190 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_POL))) |
191 (sclkpol << (cs + MXC_CSPICON_POL));
Markus Niebel5d584cc2014-02-17 17:33:17 +0100192 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_CTL))) |
193 (sclkctl << (cs + MXC_CSPICON_CTL));
Stefano Babicd205ddc2010-04-04 22:43:38 +0200194 reg_config = (reg_config & ~(1 << (cs + MXC_CSPICON_PHA))) |
195 (sclkpha << (cs + MXC_CSPICON_PHA));
196
197 debug("reg_ctrl = 0x%x\n", reg_ctrl);
Stefano Babicac87c172011-01-19 22:46:33 +0000198 reg_write(&regs->ctrl, reg_ctrl);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200199 debug("reg_config = 0x%x\n", reg_config);
Stefano Babicac87c172011-01-19 22:46:33 +0000200 reg_write(&regs->cfg, reg_config);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200201
202 /* save config register and control register */
203 mxcs->ctrl_reg = reg_ctrl;
204 mxcs->cfg_reg = reg_config;
205
206 /* clear interrupt reg */
Stefano Babicac87c172011-01-19 22:46:33 +0000207 reg_write(&regs->intr, 0);
208 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200209
210 return 0;
211}
212#endif
213
Stefano Babic2f721d12010-08-20 12:05:03 +0200214int spi_xchg_single(struct spi_slave *slave, unsigned int bitlen,
215 const u8 *dout, u8 *din, unsigned long flags)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200216{
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200217 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
Axel Lin9675fed2013-06-14 21:13:32 +0800218 int nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200219 u32 data, cnt, i;
Stefano Babicac87c172011-01-19 22:46:33 +0000220 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Heiko Schocherf659b572014-07-14 10:22:11 +0200221 u32 ts;
222 int status;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200223
Stefano Babic2f721d12010-08-20 12:05:03 +0200224 debug("%s: bitlen %d dout 0x%x din 0x%x\n",
225 __func__, bitlen, (u32)dout, (u32)din);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200226
227 mxcs->ctrl_reg = (mxcs->ctrl_reg &
228 ~MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS)) |
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100229 MXC_CSPICTRL_BITCOUNT(bitlen - 1);
230
Stefano Babicac87c172011-01-19 22:46:33 +0000231 reg_write(&regs->ctrl, mxcs->ctrl_reg | MXC_CSPICTRL_EN);
Eric Nelson08c61a52012-01-31 07:52:03 +0000232#ifdef MXC_ECSPI
Stefano Babicac87c172011-01-19 22:46:33 +0000233 reg_write(&regs->cfg, mxcs->cfg_reg);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200234#endif
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200235
Stefano Babicd205ddc2010-04-04 22:43:38 +0200236 /* Clear interrupt register */
Stefano Babicac87c172011-01-19 22:46:33 +0000237 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100238
Stefano Babic2f721d12010-08-20 12:05:03 +0200239 /*
240 * The SPI controller works only with words,
241 * check if less than a word is sent.
242 * Access to the FIFO is only 32 bit
243 */
244 if (bitlen % 32) {
245 data = 0;
246 cnt = (bitlen % 32) / 8;
247 if (dout) {
248 for (i = 0; i < cnt; i++) {
249 data = (data << 8) | (*dout++ & 0xFF);
250 }
251 }
252 debug("Sending SPI 0x%x\n", data);
253
Stefano Babicac87c172011-01-19 22:46:33 +0000254 reg_write(&regs->txdata, data);
Stefano Babic2f721d12010-08-20 12:05:03 +0200255 nbytes -= cnt;
256 }
257
258 data = 0;
259
260 while (nbytes > 0) {
261 data = 0;
262 if (dout) {
263 /* Buffer is not 32-bit aligned */
264 if ((unsigned long)dout & 0x03) {
265 data = 0;
Anatolij Gustschindff01092011-01-20 07:53:06 +0000266 for (i = 0; i < 4; i++)
Stefano Babic2f721d12010-08-20 12:05:03 +0200267 data = (data << 8) | (*dout++ & 0xFF);
Stefano Babic2f721d12010-08-20 12:05:03 +0200268 } else {
269 data = *(u32 *)dout;
270 data = cpu_to_be32(data);
Timo Herbrecher6d5ce1b2013-10-16 00:05:09 +0530271 dout += 4;
Stefano Babic2f721d12010-08-20 12:05:03 +0200272 }
Stefano Babic2f721d12010-08-20 12:05:03 +0200273 }
274 debug("Sending SPI 0x%x\n", data);
Stefano Babicac87c172011-01-19 22:46:33 +0000275 reg_write(&regs->txdata, data);
Stefano Babic2f721d12010-08-20 12:05:03 +0200276 nbytes -= 4;
277 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200278
Stefano Babicd205ddc2010-04-04 22:43:38 +0200279 /* FIFO is written, now starts the transfer setting the XCH bit */
Stefano Babicac87c172011-01-19 22:46:33 +0000280 reg_write(&regs->ctrl, mxcs->ctrl_reg |
Stefano Babicd205ddc2010-04-04 22:43:38 +0200281 MXC_CSPICTRL_EN | MXC_CSPICTRL_XCH);
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200282
Heiko Schocherf659b572014-07-14 10:22:11 +0200283 ts = get_timer(0);
284 status = reg_read(&regs->stat);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200285 /* Wait until the TC (Transfer completed) bit is set */
Heiko Schocherf659b572014-07-14 10:22:11 +0200286 while ((status & MXC_CSPICTRL_TC) == 0) {
287 if (get_timer(ts) > CONFIG_SYS_SPI_MXC_WAIT) {
288 printf("spi_xchg_single: Timeout!\n");
289 return -1;
290 }
291 status = reg_read(&regs->stat);
292 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200293
Stefano Babicd205ddc2010-04-04 22:43:38 +0200294 /* Transfer completed, clear any pending request */
Stefano Babicac87c172011-01-19 22:46:33 +0000295 reg_write(&regs->stat, MXC_CSPICTRL_TC | MXC_CSPICTRL_RXOVF);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100296
Axel Lin9675fed2013-06-14 21:13:32 +0800297 nbytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babicd205ddc2010-04-04 22:43:38 +0200298
Stefano Babic2f721d12010-08-20 12:05:03 +0200299 cnt = nbytes % 32;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200300
Stefano Babic2f721d12010-08-20 12:05:03 +0200301 if (bitlen % 32) {
Stefano Babicac87c172011-01-19 22:46:33 +0000302 data = reg_read(&regs->rxdata);
Stefano Babic2f721d12010-08-20 12:05:03 +0200303 cnt = (bitlen % 32) / 8;
Anatolij Gustschindff01092011-01-20 07:53:06 +0000304 data = cpu_to_be32(data) >> ((sizeof(data) - cnt) * 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200305 debug("SPI Rx unaligned: 0x%x\n", data);
306 if (din) {
Anatolij Gustschindff01092011-01-20 07:53:06 +0000307 memcpy(din, &data, cnt);
308 din += cnt;
Stefano Babic2f721d12010-08-20 12:05:03 +0200309 }
310 nbytes -= cnt;
311 }
312
313 while (nbytes > 0) {
314 u32 tmp;
Stefano Babicac87c172011-01-19 22:46:33 +0000315 tmp = reg_read(&regs->rxdata);
Stefano Babic2f721d12010-08-20 12:05:03 +0200316 data = cpu_to_be32(tmp);
317 debug("SPI Rx: 0x%x 0x%x\n", tmp, data);
Masahiro Yamadab4141192014-11-07 03:03:31 +0900318 cnt = min_t(u32, nbytes, sizeof(data));
Stefano Babic2f721d12010-08-20 12:05:03 +0200319 if (din) {
320 memcpy(din, &data, cnt);
321 din += cnt;
322 }
323 nbytes -= cnt;
324 }
325
326 return 0;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200327
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200328}
329
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200330int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
331 void *din, unsigned long flags)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200332{
Axel Lin9675fed2013-06-14 21:13:32 +0800333 int n_bytes = DIV_ROUND_UP(bitlen, 8);
Stefano Babic2f721d12010-08-20 12:05:03 +0200334 int n_bits;
335 int ret;
336 u32 blk_size;
337 u8 *p_outbuf = (u8 *)dout;
338 u8 *p_inbuf = (u8 *)din;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200339
Stefano Babic2f721d12010-08-20 12:05:03 +0200340 if (!slave)
341 return -1;
342
343 if (flags & SPI_XFER_BEGIN)
344 spi_cs_activate(slave);
345
346 while (n_bytes > 0) {
Stefano Babic2f721d12010-08-20 12:05:03 +0200347 if (n_bytes < MAX_SPI_BYTES)
348 blk_size = n_bytes;
349 else
350 blk_size = MAX_SPI_BYTES;
351
352 n_bits = blk_size * 8;
353
354 ret = spi_xchg_single(slave, n_bits, p_outbuf, p_inbuf, 0);
355
356 if (ret)
357 return ret;
358 if (dout)
359 p_outbuf += blk_size;
360 if (din)
361 p_inbuf += blk_size;
362 n_bytes -= blk_size;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200363 }
364
Stefano Babic2f721d12010-08-20 12:05:03 +0200365 if (flags & SPI_XFER_END) {
366 spi_cs_deactivate(slave);
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100367 }
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200368
369 return 0;
370}
371
372void spi_init(void)
373{
374}
375
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300376/*
377 * Some SPI devices require active chip-select over multiple
378 * transactions, we achieve this using a GPIO. Still, the SPI
379 * controller has to be configured to use one of its own chipselects.
380 * To use this feature you have to implement board_spi_cs_gpio() to assign
381 * a gpio value for each cs (-1 if cs doesn't need to use gpio).
382 * You must use some unused on this SPI controller cs between 0 and 3.
383 */
384static int setup_cs_gpio(struct mxc_spi_slave *mxcs,
385 unsigned int bus, unsigned int cs)
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100386{
387 int ret;
388
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300389 mxcs->gpio = board_spi_cs_gpio(bus, cs);
390 if (mxcs->gpio == -1)
391 return 0;
392
393 ret = gpio_direction_output(mxcs->gpio, !(mxcs->ss_pol));
394 if (ret) {
395 printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
396 return -EINVAL;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100397 }
398
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300399 return 0;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100400}
401
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200402struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
403 unsigned int max_hz, unsigned int mode)
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200404{
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200405 struct mxc_spi_slave *mxcs;
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100406 int ret;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200407
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100408 if (bus >= ARRAY_SIZE(spi_bases))
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200409 return NULL;
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200410
Markus Niebel027a9a02014-10-23 16:09:39 +0200411 if (max_hz == 0) {
412 printf("Error: desired clock is 0\n");
413 return NULL;
414 }
415
Simon Glassd3504fe2013-03-18 19:23:40 +0000416 mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs);
Stefano Babic2f721d12010-08-20 12:05:03 +0200417 if (!mxcs) {
418 puts("mxc_spi: SPI Slave not allocated !\n");
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100419 return NULL;
Stefano Babic2f721d12010-08-20 12:05:03 +0200420 }
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100421
Fabio Estevamde5bf022012-11-15 11:23:23 +0000422 mxcs->ss_pol = (mode & SPI_CS_HIGH) ? 1 : 0;
423
Nikita Kiryanov155fa9a2014-08-20 15:08:50 +0300424 ret = setup_cs_gpio(mxcs, bus, cs);
Guennadi Liakhovetskifc7a93c2009-02-13 09:26:40 +0100425 if (ret < 0) {
426 free(mxcs);
427 return NULL;
428 }
429
Stefano Babicd205ddc2010-04-04 22:43:38 +0200430 mxcs->base = spi_bases[bus];
Markus Niebel027a9a02014-10-23 16:09:39 +0200431 mxcs->max_hz = max_hz;
432 mxcs->mode = mode;
Stefano Babicd205ddc2010-04-04 22:43:38 +0200433
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200434 return &mxcs->slave;
435}
436
437void spi_free_slave(struct spi_slave *slave)
438{
Guennadi Liakhovetskif9b6a152009-02-07 00:09:12 +0100439 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
440
441 free(mxcs);
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200442}
443
444int spi_claim_bus(struct spi_slave *slave)
445{
Markus Niebel027a9a02014-10-23 16:09:39 +0200446 int ret;
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200447 struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
Stefano Babicac87c172011-01-19 22:46:33 +0000448 struct cspi_regs *regs = (struct cspi_regs *)mxcs->base;
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200449
Stefano Babicac87c172011-01-19 22:46:33 +0000450 reg_write(&regs->rxdata, 1);
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200451 udelay(1);
Markus Niebel027a9a02014-10-23 16:09:39 +0200452 ret = spi_cfg_mxc(mxcs, slave->cs);
453 if (ret) {
454 printf("mxc_spi: cannot setup SPI controller\n");
455 return ret;
456 }
Stefano Babicac87c172011-01-19 22:46:33 +0000457 reg_write(&regs->period, MXC_CSPIPERIOD_32KHZ);
458 reg_write(&regs->intr, 0);
Guennadi Liakhovetski38254f42008-04-15 14:14:25 +0200459
460 return 0;
461}
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200462
463void spi_release_bus(struct spi_slave *slave)
464{
465 /* TODO: Shut the controller down */
466}