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Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +02001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
Detlev Zundel792a09e2009-05-13 10:54:10 +02005 * Gary Jennejohn <garyj@denx.de>
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +02006 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * (C) Copyright 2008
9 * Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
10 *
11 * Configuation settings for the SAMSUNG SMDK6400(mDirac-III) board.
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35/*
36 * High Level Configuration Options
37 * (easy to change)
38 */
39#define CONFIG_S3C6400 1 /* in a SAMSUNG S3C6400 SoC */
40#define CONFIG_S3C64XX 1 /* in a SAMSUNG S3C64XX Family */
41#define CONFIG_SMDK6400 1 /* on a SAMSUNG SMDK6400 Board */
42
Cyril Chemparathy678e0082010-06-07 14:13:27 -040043#define CONFIG_SKIP_RELOCATE_UBOOT
44
45#define CONFIG_PERIPORT_REMAP
46#define CONFIG_PERIPORT_BASE 0x70000000
47#define CONFIG_PERIPORT_SIZE 0x13
48
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_SDRAM_BASE 0x50000000
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +020050
51/* input clock of PLL: SMDK6400 has 12MHz input clock */
52#define CONFIG_SYS_CLK_FREQ 12000000
53
54#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
55#define CONFIG_ENABLE_MMU
56#endif
57
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +020058#define CONFIG_SETUP_MEMORY_TAGS
59#define CONFIG_CMDLINE_TAG
60#define CONFIG_INITRD_TAG
61
62/*
63 * Architecture magic and machine type
64 */
65#define MACH_TYPE 1270
66
67#define CONFIG_DISPLAY_CPUINFO
68#define CONFIG_DISPLAY_BOARDINFO
69
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +020070/*
71 * Size of malloc() pool
72 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
74#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for initial data */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +020075
76/*
77 * Hardware drivers
78 */
Ben Warrenb1c0eaa2009-08-25 13:09:37 -070079#define CONFIG_NET_MULTI
80#define CONFIG_CS8900 /* we have a CS8900 on-board */
81#define CONFIG_CS8900_BASE 0x18800300
82#define CONFIG_CS8900_BUS16 /* follow the Linux driver */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +020083
84/*
85 * select serial console configuration
86 */
87#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK6400 */
88
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020089#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
90#ifdef CONFIG_SYS_HUSH_PARSER
91#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +020092#endif
93
94#define CONFIG_CMDLINE_EDITING
95
96/* allow to overwrite serial and ethaddr */
97#define CONFIG_ENV_OVERWRITE
98
99#define CONFIG_BAUDRATE 115200
100
101/***********************************************************
102 * Command definition
103 ***********************************************************/
104#include <config_cmd_default.h>
105
106#define CONFIG_CMD_CACHE
107#define CONFIG_CMD_REGINFO
108#define CONFIG_CMD_LOADS
109#define CONFIG_CMD_LOADB
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500110#define CONFIG_CMD_SAVEENV
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200111#define CONFIG_CMD_NAND
112#if defined(CONFIG_BOOT_ONENAND)
113#define CONFIG_CMD_ONENAND
114#endif
115#define CONFIG_CMD_PING
116#define CONFIG_CMD_ELF
117#define CONFIG_CMD_FAT
118#define CONFIG_CMD_EXT2
119
120#define CONFIG_BOOTDELAY 3
121
122#define CONFIG_ZERO_BOOTDELAY_CHECK
123
124#if (CONFIG_COMMANDS & CONFIG_CMD_KGDB)
125#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
126#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
127#endif
128
129/*
130 * Miscellaneous configurable options
131 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_LONGHELP /* undef to save memory */
133#define CONFIG_SYS_PROMPT "SMDK6400 # " /* Monitor Command Prompt */
134#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
135#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
136#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
137#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* memtest works on */
140#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x7e00000) /* 126MB in DRAM */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* default load address */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_HZ 1000
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200145
146/* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200148
149/*-----------------------------------------------------------------------
150 * Stack sizes
151 *
152 * The stack sizes are set up in start.S using the settings below
153 */
154#define CONFIG_STACKSIZE 0x40000 /* regular stack 256KB */
155
156/**********************************
157 Support Clock Settings
158 **********************************
159 Setting SYNC ASYNC
160 ----------------------------------
161 667_133_66 X O
162 533_133_66 O O
163 400_133_66 X O
164 400_100_50 O O
165 **********************************/
166
167/*#define CONFIG_CLK_667_133_66*/
168#define CONFIG_CLK_533_133_66
169/*
170#define CONFIG_CLK_400_100_50
171#define CONFIG_CLK_400_133_66
172#define CONFIG_SYNC_MODE
173*/
174
175/* SMDK6400 has 2 banks of DRAM, but we use only one in U-Boot */
176#define CONFIG_NR_DRAM_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200178#define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB in Bank #1 */
179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_FLASH_BASE 0x10000000
181#define CONFIG_SYS_MONITOR_BASE 0x00000000
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200182
183/*-----------------------------------------------------------------------
184 * FLASH and environment organization
185 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200187/* AM29LV160B has 35 sectors, AM29LV800B - 19 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_MAX_FLASH_SECT 40
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200189
190#define CONFIG_AMD_LV800
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_FLASH_CFI 1 /* Use CFI parameters (needed?) */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200192/* Use drivers/cfi_flash.c, even though the flash is not CFI-compliant */
Jean-Christophe PLAGNIOL-VILLARDf9f692e2008-08-31 00:39:48 +0200193#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200195#define CONFIG_FLASH_CFI_LEGACY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_FLASH_LEGACY_512Kx16
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200197
198/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_FLASH_ERASE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
200#define CONFIG_SYS_FLASH_WRITE_TOUT (5 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200201
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200202#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200203
204/*
205 * SMDK6400 board specific data
206 */
207
208#define CONFIG_IDENT_STRING " for SMDK6400"
209
210/* base address for uboot */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_PHY_UBOOT_BASE (CONFIG_SYS_SDRAM_BASE + 0x07e00000)
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200212/* total memory available to uboot */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_UBOOT_SIZE (1024 * 1024)
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200214
Guennadi Liakhovetskib74ab732009-05-18 16:07:22 +0200215/* Put environment copies after the end of U-Boot owned RAM */
216#define CONFIG_NAND_ENV_DST (CONFIG_SYS_UBOOT_BASE + CONFIG_SYS_UBOOT_SIZE)
217
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200218#ifdef CONFIG_ENABLE_MMU
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200220#define CONFIG_BOOTCOMMAND "nand read 0xc0018000 0x60000 0x1c0000;" \
221 "bootm 0xc0018000"
222#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200224#define CONFIG_BOOTCOMMAND "nand read 0x50018000 0x60000 0x1c0000;" \
225 "bootm 0x50018000"
226#endif
227
228/* NAND U-Boot load and start address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_MAPPED_RAM_BASE + 0x07e00000)
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200230
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200231#define CONFIG_ENV_OFFSET 0x0040000
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200232
233/* NAND configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_MAX_NAND_DEVICE 1
235#define CONFIG_SYS_NAND_BASE 0x70200010
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_S3C_NAND_HWECC
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
239#define CONFIG_SYS_NAND_WP 1
240#define CONFIG_SYS_NAND_YAFFS_WRITE 1 /* support yaffs write */
241#define CONFIG_SYS_NAND_BBT_2NDPAGE 1 /* bad-block markers in 1st and 2nd pages */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_PHY_UBOOT_BASE /* NUB load-addr */
244#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* NUB start-addr */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_NAND_U_BOOT_OFFS (4 * 1024) /* Offset to RAM U-Boot image */
247#define CONFIG_SYS_NAND_U_BOOT_SIZE (252 * 1024) /* Size of RAM U-Boot image */
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200248
249/* NAND chip page size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_NAND_PAGE_SIZE 2048
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200251/* NAND chip block size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200253/* NAND chip page per block count */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_NAND_PAGE_COUNT 64
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200255/* Location of the bad-block label */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200257/* Extra address cycle for > 128MiB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_NAND_5_ADDR_CYCLE
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200259
260/* Size of the block protected by one OOB (Spare Area in Samsung terminology) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_NAND_ECCSIZE CONFIG_SYS_NAND_PAGE_SIZE
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200262/* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200263#define CONFIG_SYS_NAND_ECCBYTES 4
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200264/* Number of ECC-blocks per NAND page */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200266/* Size of a single OOB region */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_NAND_OOBSIZE 64
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200268/* Number of ECC bytes per page */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200270/* ECC byte positions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200272 48, 49, 50, 51, 52, 53, 54, 55, \
273 56, 57, 58, 59, 60, 61, 62, 63}
274
275/* Boot configuration (define only one of next 3) */
276#define CONFIG_BOOT_NAND
277/* None of these are currently implemented. Left from the original Samsung
278 * version for reference
279#define CONFIG_BOOT_NOR
280#define CONFIG_BOOT_MOVINAND
281#define CONFIG_BOOT_ONENAND
282*/
283
284#define CONFIG_NAND
285#define CONFIG_NAND_S3C64XX
286/* Unimplemented or unsupported. See comment above.
287#define CONFIG_ONENAND
288#define CONFIG_MOVINAND
289*/
290
291/* Settings as above boot configuration */
Jean-Christophe PLAGNIOL-VILLARD51bfee12008-09-10 22:47:58 +0200292#define CONFIG_ENV_IS_IN_NAND
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200293#define CONFIG_BOOTARGS "console=ttySAC,115200"
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200294
295#if !defined(CONFIG_ENABLE_MMU)
296#define CONFIG_CMD_USB 1
Jean-Christophe PLAGNIOL-VILLARD6d27bca2009-03-29 23:01:42 +0200297#define CONFIG_USB_S3C64XX
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200298#define CONFIG_USB_OHCI_NEW 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x74300000
300#define CONFIG_SYS_USB_OHCI_SLOT_NAME "s3c6400"
301#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
302#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
Guennadi Liakhovetski11edcfe2008-08-31 00:39:47 +0200303
304#define CONFIG_USB_STORAGE 1
305#endif
306#define CONFIG_DOS_PARTITION 1
307
308#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_ENABLE_MMU)
309# error "usb_ohci.c is currently broken with MMU enabled."
310#endif
311
312#endif /* __CONFIG_H */