| Otavio Salvador | 4579dc3 | 2015-02-17 10:42:46 -0200 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (C) 2014, 2015 O.S. Systems Software LTDA. |
| 3 | * Copyright (C) 2014 Kynetics LLC. |
| 4 | * Copyright (C) 2014 Revolution Robotics, Inc. |
| 5 | * |
| 6 | * Author: Otavio Salvador <otavio@ossystems.com.br> |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/iomux.h> |
| 13 | #include <asm/arch/imx-regs.h> |
| 14 | #include <asm/arch/mx6-pins.h> |
| 15 | #include <asm/arch/sys_proto.h> |
| 16 | #include <asm/gpio.h> |
| 17 | #include <asm/imx-common/iomux-v3.h> |
| 18 | #include <asm/io.h> |
| 19 | #include <linux/sizes.h> |
| 20 | #include <common.h> |
| 21 | #include <watchdog.h> |
| 22 | #include <fsl_esdhc.h> |
| 23 | #include <mmc.h> |
| 24 | |
| 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
| 27 | #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ |
| 28 | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ |
| 29 | PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ |
| 30 | PAD_CTL_LVE) |
| 31 | |
| 32 | #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \ |
| 33 | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ |
| 34 | PAD_CTL_SRE_FAST | PAD_CTL_HYS | \ |
| 35 | PAD_CTL_LVE) |
| 36 | |
| 37 | int dram_init(void) |
| 38 | { |
| 39 | gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); |
| 40 | |
| 41 | return 0; |
| 42 | } |
| 43 | |
| 44 | static void setup_iomux_uart(void) |
| 45 | { |
| 46 | static iomux_v3_cfg_t const uart1_pads[] = { |
| 47 | MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 48 | MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 49 | }; |
| 50 | |
| 51 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); |
| 52 | } |
| 53 | |
| 54 | static struct fsl_esdhc_cfg usdhc_cfg[1] = { |
| 55 | {USDHC2_BASE_ADDR}, |
| 56 | }; |
| 57 | |
| 58 | int board_mmc_getcd(struct mmc *mmc) |
| 59 | { |
| 60 | return 1; /* Assume boot SD always present */ |
| 61 | } |
| 62 | |
| 63 | int board_mmc_init(bd_t *bis) |
| 64 | { |
| 65 | static iomux_v3_cfg_t const usdhc2_pads[] = { |
| 66 | MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 67 | MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 68 | MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 69 | MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 70 | MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 71 | MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 72 | MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 73 | MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 74 | MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 75 | MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 76 | MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), |
| 77 | }; |
| 78 | |
| 79 | imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); |
| 80 | |
| 81 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); |
| 82 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); |
| 83 | } |
| 84 | |
| 85 | int board_early_init_f(void) |
| 86 | { |
| 87 | setup_iomux_uart(); |
| 88 | return 0; |
| 89 | } |
| 90 | |
| 91 | int board_init(void) |
| 92 | { |
| 93 | /* address of boot parameters */ |
| 94 | gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; |
| 95 | |
| 96 | return 0; |
| 97 | } |
| 98 | |
| 99 | int board_late_init(void) |
| 100 | { |
| 101 | #ifdef CONFIG_HW_WATCHDOG |
| 102 | hw_watchdog_init(); |
| 103 | #endif |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | int checkboard(void) |
| 109 | { |
| 110 | puts("Board: WaRP Board\n"); |
| 111 | |
| 112 | return 0; |
| 113 | } |