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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 457faef262c5c9533c344f25eafb10e757149a34 / . / arch / arm / dts / k3-j721e-main.dtsi
blob: 45ac98c47ed37f5aff21ae52572daa17b657a230 [file] [log] [blame]
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for J721E SoC Family Main Domain peripherals
4 *
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
6 */
7
8&cbass_main {
9 msmc_ram: sram@70000000 {
10 compatible = "mmio-sram";
11 reg = <0x0 0x70000000 0x0 0x800000>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14 ranges = <0x0 0x0 0x70000000 0x800000>;
15
16 atf-sram@0 {
17 reg = <0x0 0x20000>;
18 };
19 };
20
21 gic500: interrupt-controller@1800000 {
22 compatible = "arm,gic-v3";
23 #address-cells = <2>;
24 #size-cells = <2>;
25 ranges;
26 #interrupt-cells = <3>;
27 interrupt-controller;
28 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
29 <0x00 0x01900000 0x00 0x100000>; /* GICR */
30
31 /* vcpumntirq: virtual CPU interface maintenance interrupt */
32 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
33
34 gic_its: gic-its@18200000 {
35 compatible = "arm,gic-v3-its";
36 reg = <0x00 0x01820000 0x00 0x10000>;
37 socionext,synquacer-pre-its = <0x1000000 0x400000>;
38 msi-controller;
39 #msi-cells = <1>;
40 };
41 };
42
43 smmu0: smmu@36600000 {
44 compatible = "arm,smmu-v3";
45 reg = <0x0 0x36600000 0x0 0x100000>;
46 interrupt-parent = <&gic500>;
47 interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
48 <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
49 interrupt-names = "eventq", "gerror";
50 #iommu-cells = <1>;
51 };
52
53 secure_proxy_main: mailbox@32c00000 {
54 compatible = "ti,am654-secure-proxy";
55 #mbox-cells = <1>;
56 reg-names = "target_data", "rt", "scfg";
57 reg = <0x00 0x32c00000 0x00 0x100000>,
58 <0x00 0x32400000 0x00 0x100000>,
59 <0x00 0x32800000 0x00 0x100000>;
60 interrupt-names = "rx_011";
61 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
62 };
63
64 main_pmx0: pinmux@11c000 {
65 compatible = "pinctrl-single";
66 /* Proxy 0 addressing */
67 reg = <0x0 0x11c000 0x0 0x2b4>;
68 #pinctrl-cells = <1>;
69 pinctrl-single,register-width = <32>;
70 pinctrl-single,function-mask = <0xffffffff>;
71 };
72
73 main_uart0: serial@2800000 {
74 compatible = "ti,j721e-uart", "ti,am654-uart";
75 reg = <0x00 0x02800000 0x00 0x100>;
76 reg-shift = <2>;
77 reg-io-width = <4>;
78 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
79 clock-frequency = <48000000>;
80 current-speed = <115200>;
81 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
82 clocks = <&k3_clks 146 0>;
83 clock-names = "fclk";
84 };
85
86 main_uart1: serial@2810000 {
87 compatible = "ti,j721e-uart", "ti,am654-uart";
88 reg = <0x00 0x02810000 0x00 0x100>;
89 reg-shift = <2>;
90 reg-io-width = <4>;
91 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
92 clock-frequency = <48000000>;
93 current-speed = <115200>;
94 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
95 clocks = <&k3_clks 278 0>;
96 clock-names = "fclk";
97 };
98
99 main_uart2: serial@2820000 {
100 compatible = "ti,j721e-uart", "ti,am654-uart";
101 reg = <0x00 0x02820000 0x00 0x100>;
102 reg-shift = <2>;
103 reg-io-width = <4>;
104 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
105 clock-frequency = <48000000>;
106 current-speed = <115200>;
107 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
108 clocks = <&k3_clks 279 0>;
109 clock-names = "fclk";
110 };
111
112 main_uart3: serial@2830000 {
113 compatible = "ti,j721e-uart", "ti,am654-uart";
114 reg = <0x00 0x02830000 0x00 0x100>;
115 reg-shift = <2>;
116 reg-io-width = <4>;
117 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
118 clock-frequency = <48000000>;
119 current-speed = <115200>;
120 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
121 clocks = <&k3_clks 280 0>;
122 clock-names = "fclk";
123 };
124
125 main_uart4: serial@2840000 {
126 compatible = "ti,j721e-uart", "ti,am654-uart";
127 reg = <0x00 0x02840000 0x00 0x100>;
128 reg-shift = <2>;
129 reg-io-width = <4>;
130 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
131 clock-frequency = <48000000>;
132 current-speed = <115200>;
133 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
134 clocks = <&k3_clks 281 0>;
135 clock-names = "fclk";
136 };
137
138 main_uart5: serial@2850000 {
139 compatible = "ti,j721e-uart", "ti,am654-uart";
140 reg = <0x00 0x02850000 0x00 0x100>;
141 reg-shift = <2>;
142 reg-io-width = <4>;
143 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
144 clock-frequency = <48000000>;
145 current-speed = <115200>;
146 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
147 clocks = <&k3_clks 282 0>;
148 clock-names = "fclk";
149 };
150
151 main_uart6: serial@2860000 {
152 compatible = "ti,j721e-uart", "ti,am654-uart";
153 reg = <0x00 0x02860000 0x00 0x100>;
154 reg-shift = <2>;
155 reg-io-width = <4>;
156 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
157 clock-frequency = <48000000>;
158 current-speed = <115200>;
159 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
160 clocks = <&k3_clks 283 0>;
161 clock-names = "fclk";
162 };
163
164 main_uart7: serial@2870000 {
165 compatible = "ti,j721e-uart", "ti,am654-uart";
166 reg = <0x00 0x02870000 0x00 0x100>;
167 reg-shift = <2>;
168 reg-io-width = <4>;
169 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
170 clock-frequency = <48000000>;
171 current-speed = <115200>;
172 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
173 clocks = <&k3_clks 284 0>;
174 clock-names = "fclk";
175 };
176
177 main_uart8: serial@2880000 {
178 compatible = "ti,j721e-uart", "ti,am654-uart";
179 reg = <0x00 0x02880000 0x00 0x100>;
180 reg-shift = <2>;
181 reg-io-width = <4>;
182 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
183 clock-frequency = <48000000>;
184 current-speed = <115200>;
185 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
186 clocks = <&k3_clks 285 0>;
187 clock-names = "fclk";
188 };
189
190 main_uart9: serial@2890000 {
191 compatible = "ti,j721e-uart", "ti,am654-uart";
192 reg = <0x00 0x02890000 0x00 0x100>;
193 reg-shift = <2>;
194 reg-io-width = <4>;
195 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
196 clock-frequency = <48000000>;
197 current-speed = <115200>;
198 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
199 clocks = <&k3_clks 286 0>;
200 clock-names = "fclk";
201 };
202
Faiz Abbas16217ed2020-01-28 15:40:04 +0530[diff] [blame]203 main_gpio0: gpio@600000 {
204 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
205 reg = <0x0 0x00600000 0x0 0x100>;
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupts = <105 0 IRQ_TYPE_EDGE_RISING>,
209 <105 1 IRQ_TYPE_EDGE_RISING>,
210 <105 2 IRQ_TYPE_EDGE_RISING>,
211 <105 3 IRQ_TYPE_EDGE_RISING>,
212 <105 4 IRQ_TYPE_EDGE_RISING>,
213 <105 5 IRQ_TYPE_EDGE_RISING>,
214 <105 6 IRQ_TYPE_EDGE_RISING>,
215 <105 7 IRQ_TYPE_EDGE_RISING>;
216 interrupt-controller;
217 #interrupt-cells = <2>;
218 ti,ngpio = <128>;
219 ti,davinci-gpio-unbanked = <0>;
220 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
221 clocks = <&k3_clks 105 0>;
222 clock-names = "gpio";
223 };
224
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]225 main_sdhci0: sdhci@4f80000 {
226 compatible = "ti,j721e-sdhci-8bit";
227 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
228 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
229 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
230 clock-names = "clk_xin", "clk_ahb";
231 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
232 assigned-clocks = <&k3_clks 91 1>;
233 assigned-clock-parents = <&k3_clks 91 2>;
234 bus-width = <8>;
235 ti,otap-del-sel = <0x2>;
236 ti,trm-icp = <0x8>;
237 dma-coherent;
238 };
239
240 main_sdhci1: sdhci@4fb0000 {
241 compatible = "ti,j721e-sdhci-4bit";
242 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
243 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
244 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
245 clock-names = "clk_xin", "clk_ahb";
246 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
247 assigned-clocks = <&k3_clks 92 0>;
248 assigned-clock-parents = <&k3_clks 92 1>;
249 ti,otap-del-sel = <0x2>;
250 ti,trm-icp = <0x8>;
251 dma-coherent;
252 };
Lokesh Vutla55f8eb32019-09-04 16:01:38 +0530[diff] [blame]253
254 main_r5fss0: r5fss@5c00000 {
255 compatible = "ti,j721e-r5fss";
256 lockstep-mode = <0>;
257 #address-cells = <1>;
258 #size-cells = <1>;
259 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
260 <0x5d00000 0x00 0x5d00000 0x20000>;
261 power-domains = <&k3_pds 243 TI_SCI_PD_EXCLUSIVE>;
262
263 main_r5fss0_core0: r5f@5c00000 {
264 compatible = "ti,j721e-r5f";
265 reg = <0x5c00000 0x00008000>,
266 <0x5c10000 0x00008000>;
267 reg-names = "atcm", "btcm";
268 ti,sci = <&dmsc>;
269 ti,sci-dev-id = <245>;
270 ti,sci-proc-ids = <0x06 0xFF>;
271 resets = <&k3_reset 245 1>;
272 atcm-enable = <1>;
273 btcm-enable = <1>;
274 loczrama = <1>;
275 };
276
277 main_r5fss0_core1: r5f@5d00000 {
278 compatible = "ti,j721e-r5f";
279 reg = <0x5d00000 0x00008000>,
280 <0x5d10000 0x00008000>;
281 reg-names = "atcm", "btcm";
282 ti,sci = <&dmsc>;
283 ti,sci-dev-id = <246>;
284 ti,sci-proc-ids = <0x07 0xFF>;
285 resets = <&k3_reset 246 1>;
286 atcm-enable = <1>;
287 btcm-enable = <1>;
288 loczrama = <1>;
289 };
290 };
291
292 main_r5fss1: r5fss@5e00000 {
293 compatible = "ti,j721e-r5fss";
294 lockstep-mode = <1>;
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
298 <0x5f00000 0x00 0x5f00000 0x20000>;
299 power-domains = <&k3_pds 244 TI_SCI_PD_EXCLUSIVE>;
300
301 main_r5fss1_core0: r5f@5e00000 {
302 compatible = "ti,j721e-r5f";
303 reg = <0x5e00000 0x00008000>,
304 <0x5e10000 0x00008000>;
305 reg-names = "atcm", "btcm";
306 ti,sci = <&dmsc>;
307 ti,sci-dev-id = <247>;
308 ti,sci-proc-ids = <0x08 0xFF>;
309 resets = <&k3_reset 247 1>;
310 atcm-enable = <1>;
311 btcm-enable = <1>;
312 loczrama = <1>;
313 };
314
315 main_r5fss1_core1: r5f@5f00000 {
316 compatible = "ti,j721e-r5f";
317 reg = <0x5f00000 0x00008000>,
318 <0x5f10000 0x00008000>;
319 reg-names = "atcm", "btcm";
320 ti,sci = <&dmsc>;
321 ti,sci-dev-id = <248>;
322 ti,sci-proc-ids = <0x09 0xFF>;
323 resets = <&k3_reset 248 1>;
324 atcm-enable = <1>;
325 btcm-enable = <1>;
326 loczrama = <1>;
327 };
328 };
Lokesh Vutla293e3972019-09-04 16:01:39 +0530[diff] [blame]329
330 c66_0: dsp@4d80800000 {
331 compatible = "ti,j721e-c66-dsp";
332 reg = <0x4d 0x80800000 0x00 0x00048000>,
333 <0x4d 0x80e00000 0x00 0x00008000>,
334 <0x4d 0x80f00000 0x00 0x00008000>;
335 reg-names = "l2sram", "l1pram", "l1dram";
336 ti,sci = <&dmsc>;
337 ti,sci-dev-id = <142>;
338 ti,sci-proc-ids = <0x03 0xFF>;
339 resets = <&k3_reset 142 1>;
340 };
341
342 c66_1: dsp@4d81800000 {
343 compatible = "ti,j721e-c66-dsp";
344 reg = <0x4d 0x81800000 0x00 0x00048000>,
345 <0x4d 0x81e00000 0x00 0x00008000>,
346 <0x4d 0x81f00000 0x00 0x00008000>;
347 reg-names = "l2sram", "l1pram", "l1dram";
348 ti,sci = <&dmsc>;
349 ti,sci-dev-id = <143>;
350 ti,sci-proc-ids = <0x04 0xFF>;
351 resets = <&k3_reset 143 1>;
352 };
Lokesh Vutla1b846fc2019-09-04 16:01:40 +0530[diff] [blame]353
354 c71_0: dsp@64800000 {
355 compatible = "ti,j721e-c71-dsp";
356 reg = <0x00 0x64800000 0x00 0x00080000>,
357 <0x00 0x64e00000 0x00 0x0000c000>;
358 reg-names = "l2sram", "l1dram";
359 ti,sci = <&dmsc>;
360 ti,sci-dev-id = <15>;
361 ti,sci-proc-ids = <0x30 0xFF>;
362 resets = <&k3_reset 15 1>;
363 };
Faiz Abbas991e8a52019-10-15 18:24:39 +0530[diff] [blame]364
Vignesh Raghavendra5aeab3b2019-11-18 19:16:35 +0530[diff] [blame]365 usbss0: cdns_usb@4104000 {
366 compatible = "ti,j721e-usb";
367 reg = <0x00 0x4104000 0x00 0x100>;
368 dma-coherent;
369 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
370 clocks = <&k3_clks 288 15>, <&k3_clks 288 3>;
371 clock-names = "usb2_refclk", "lpm_clk";
372 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
373 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
374 #address-cells = <2>;
375 #size-cells = <2>;
376 ranges;
377
378 phy@4108000 {
379 compatible = "ti,j721e-usb2-phy";
380 reg = <0x00 0x4108000 0x00 0x400>;
381 };
382
383 usb0: usb@6000000 {
384 compatible = "cdns,usb3";
385 reg = <0x00 0x6000000 0x00 0x10000>,
386 <0x00 0x6010000 0x00 0x10000>,
387 <0x00 0x6020000 0x00 0x10000>;
388 reg-names = "otg", "xhci", "dev";
389 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
390 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
391 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
392 interrupt-names = "host",
393 "peripheral",
394 "otg";
395 maximum-speed = "super-speed";
396 dr_mode = "otg";
397 };
398 };
399
400 usbss1: cdns_usb@4114000 {
401 compatible = "ti,j721e-usb";
402 reg = <0x00 0x4114000 0x00 0x100>;
403 dma-coherent;
404 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
405 clocks = <&k3_clks 289 15>, <&k3_clks 289 3>;
406 clock-names = "usb2_refclk", "lpm_clk";
407 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
408 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
409 #address-cells = <2>;
410 #size-cells = <2>;
411 ranges;
412
413 phy@4118000 {
414 compatible = "ti,j721e-usb2-phy";
415 reg = <0x00 0x4118000 0x00 0x400>;
416 };
417
418 usb1: usb@6400000 {
419 compatible = "cdns,usb3";
420 reg = <0x00 0x6400000 0x00 0x10000>,
421 <0x00 0x6410000 0x00 0x10000>,
422 <0x00 0x6420000 0x00 0x10000>;
423 reg-names = "otg", "xhci", "dev";
424 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
425 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
426 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
427 interrupt-names = "host",
428 "peripheral",
429 "otg";
430 maximum-speed = "super-speed";
431 dr_mode = "otg";
432 };
433 };
434
Faiz Abbas991e8a52019-10-15 18:24:39 +0530[diff] [blame]435 ufs_wrapper: ufs-wrapper@4e80000 {
436 compatible = "ti,j721e-ufs";
437 reg = <0x0 0x4e80000 0x0 0x100>;
438 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
439 clocks = <&k3_clks 277 1>;
440 assigned-clocks = <&k3_clks 277 1>;
441 assigned-clock-parents = <&k3_clks 277 4>;
442 ranges;
443 #address-cells = <2>;
444 #size-cells = <2>;
445
446 ufs@4e84000 {
447 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
448 reg = <0x0 0x4e84000 0x0 0x10000>;
449 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
450 freq-table-hz = <0 0>, <0 0>;
451 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>;
452 clock-names = "core_clk", "phy_clk";
453 assigned-clocks = <&k3_clks 277 1>;
454 assigned-clock-parents = <&k3_clks 277 4>;
455 dma-coherent;
456 };
457 };
Vignesh Raghavendra01ec6a52020-01-27 23:22:13 +0530[diff] [blame]458
459 main_i2c0: i2c@2000000 {
460 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
461 reg = <0x0 0x2000000 0x0 0x100>;
462 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465 clock-names = "fck";
466 clocks = <&k3_clks 187 0>;
467 power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
468 };
469
470 main_i2c1: i2c@2010000 {
471 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
472 reg = <0x0 0x2010000 0x0 0x100>;
473 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
474 #address-cells = <1>;
475 #size-cells = <0>;
476 clock-names = "fck";
477 clocks = <&k3_clks 188 0>;
478 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
479 };
480
481 main_i2c2: i2c@2020000 {
482 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
483 reg = <0x0 0x2020000 0x0 0x100>;
484 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
485 #address-cells = <1>;
486 #size-cells = <0>;
487 clock-names = "fck";
488 clocks = <&k3_clks 189 0>;
489 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
490 };
491
492 main_i2c3: i2c@2030000 {
493 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
494 reg = <0x0 0x2030000 0x0 0x100>;
495 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
496 #address-cells = <1>;
497 #size-cells = <0>;
498 clock-names = "fck";
499 clocks = <&k3_clks 190 0>;
500 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
501 };
502
503 main_i2c4: i2c@2040000 {
504 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
505 reg = <0x0 0x2040000 0x0 0x100>;
506 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
507 #address-cells = <1>;
508 #size-cells = <0>;
509 clock-names = "fck";
510 clocks = <&k3_clks 191 0>;
511 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
512 };
513
514 main_i2c5: i2c@2050000 {
515 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
516 reg = <0x0 0x2050000 0x0 0x100>;
517 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 clock-names = "fck";
521 clocks = <&k3_clks 192 0>;
522 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
523 };
524
525 main_i2c6: i2c@2060000 {
526 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
527 reg = <0x0 0x2060000 0x0 0x100>;
528 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
529 #address-cells = <1>;
530 #size-cells = <0>;
531 clock-names = "fck";
532 clocks = <&k3_clks 193 0>;
533 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
534 };
Lokesh Vutlaeeb2e8b2019-06-13 10:29:53 +0530[diff] [blame]535};