Gitiles
Code Review Sign In
gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 459353d43a44379509a3fc9050fa151e7abbf06e / . / arch / arm / dts / da850.dtsi
blob: c66cf78953639db3ed025e4997beb6ef77719064 [file] [log] [blame]
Adam Ford4c707552017-09-17 20:43:44 -0500[diff] [blame]1/*
2 * Copyright 2012 DENX Software Engineering GmbH
3 * Heiko Schocher <hs@denx.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#include "skeleton.dtsi"
11#include <dt-bindings/interrupt-controller/irq.h>
12
13/ {
14 arm {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
18 intc: interrupt-controller@fffee000 {
19 compatible = "ti,cp-intc";
20 interrupt-controller;
21 #interrupt-cells = <1>;
22 ti,intc-size = <101>;
23 reg = <0xfffee000 0x2000>;
24 };
25 };
Lokesh Vutla459353d2018-03-16 18:52:20 +0530[diff] [blame^]26 dsp: dsp@11800000 {
27 compatible = "ti,da850-dsp";
28 reg = <0x11800000 0x40000>,
29 <0x11e00000 0x8000>,
30 <0x11f00000 0x8000>,
31 <0x01c14044 0x4>,
32 <0x01c14174 0x8>;
33 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
34 interrupt-parent = <&intc>;
35 interrupts = <28>;
36 status = "disabled";
Adam Ford4c707552017-09-17 20:43:44 -0500[diff] [blame]37 };
Adam Ford4c707552017-09-17 20:43:44 -0500[diff] [blame]38 soc@1c00000 {
39 compatible = "simple-bus";
40 model = "da850";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges = <0x0 0x01c00000 0x400000>;
44 interrupt-parent = <&intc>;
45
46 pmx_core: pinmux@14120 {
47 compatible = "pinctrl-single";
48 reg = <0x14120 0x50>;
49 #address-cells = <1>;
50 #size-cells = <0>;
51 #pinctrl-cells = <2>;
52 pinctrl-single,bit-per-mux;
53 pinctrl-single,register-width = <32>;
54 pinctrl-single,function-mask = <0xf>;
55 status = "disabled";
56
57 serial0_rtscts_pins: pinmux_serial0_rtscts_pins {
58 pinctrl-single,bits = <
59 /* UART0_RTS UART0_CTS */
60 0x0c 0x22000000 0xff000000
61 >;
62 };
63 serial0_rxtx_pins: pinmux_serial0_rxtx_pins {
64 pinctrl-single,bits = <
65 /* UART0_TXD UART0_RXD */
66 0x0c 0x00220000 0x00ff0000
67 >;
68 };
69 serial1_rtscts_pins: pinmux_serial1_rtscts_pins {
70 pinctrl-single,bits = <
71 /* UART1_CTS UART1_RTS */
72 0x00 0x00440000 0x00ff0000
73 >;
74 };
75 serial1_rxtx_pins: pinmux_serial1_rxtx_pins {
76 pinctrl-single,bits = <
77 /* UART1_TXD UART1_RXD */
78 0x10 0x22000000 0xff000000
79 >;
80 };
81 serial2_rtscts_pins: pinmux_serial2_rtscts_pins {
82 pinctrl-single,bits = <
83 /* UART2_CTS UART2_RTS */
84 0x00 0x44000000 0xff000000
85 >;
86 };
87 serial2_rxtx_pins: pinmux_serial2_rxtx_pins {
88 pinctrl-single,bits = <
89 /* UART2_TXD UART2_RXD */
90 0x10 0x00220000 0x00ff0000
91 >;
92 };
93 i2c0_pins: pinmux_i2c0_pins {
94 pinctrl-single,bits = <
95 /* I2C0_SDA,I2C0_SCL */
96 0x10 0x00002200 0x0000ff00
97 >;
98 };
99 i2c1_pins: pinmux_i2c1_pins {
100 pinctrl-single,bits = <
101 /* I2C1_SDA, I2C1_SCL */
102 0x10 0x00440000 0x00ff0000
103 >;
104 };
105 mmc0_pins: pinmux_mmc_pins {
106 pinctrl-single,bits = <
107 /* MMCSD0_DAT[3] MMCSD0_DAT[2]
108 * MMCSD0_DAT[1] MMCSD0_DAT[0]
109 * MMCSD0_CMD MMCSD0_CLK
110 */
111 0x28 0x00222222 0x00ffffff
112 >;
113 };
114 ehrpwm0a_pins: pinmux_ehrpwm0a_pins {
115 pinctrl-single,bits = <
116 /* EPWM0A */
117 0xc 0x00000002 0x0000000f
118 >;
119 };
120 ehrpwm0b_pins: pinmux_ehrpwm0b_pins {
121 pinctrl-single,bits = <
122 /* EPWM0B */
123 0xc 0x00000020 0x000000f0
124 >;
125 };
126 ehrpwm1a_pins: pinmux_ehrpwm1a_pins {
127 pinctrl-single,bits = <
128 /* EPWM1A */
129 0x14 0x00000002 0x0000000f
130 >;
131 };
132 ehrpwm1b_pins: pinmux_ehrpwm1b_pins {
133 pinctrl-single,bits = <
134 /* EPWM1B */
135 0x14 0x00000020 0x000000f0
136 >;
137 };
138 ecap0_pins: pinmux_ecap0_pins {
139 pinctrl-single,bits = <
140 /* ECAP0_APWM0 */
141 0x8 0x20000000 0xf0000000
142 >;
143 };
144 ecap1_pins: pinmux_ecap1_pins {
145 pinctrl-single,bits = <
146 /* ECAP1_APWM1 */
147 0x4 0x40000000 0xf0000000
148 >;
149 };
150 ecap2_pins: pinmux_ecap2_pins {
151 pinctrl-single,bits = <
152 /* ECAP2_APWM2 */
153 0x4 0x00000004 0x0000000f
154 >;
155 };
156 spi0_pins: pinmux_spi0_pins {
157 pinctrl-single,bits = <
158 /* SIMO, SOMI, CLK */
159 0xc 0x00001101 0x0000ff0f
160 >;
161 };
162 spi0_cs0_pin: pinmux_spi0_cs0 {
163 pinctrl-single,bits = <
164 /* CS0 */
165 0x10 0x00000010 0x000000f0
166 >;
167 };
168 spi0_cs3_pin: pinmux_spi0_cs3_pin {
169 pinctrl-single,bits = <
170 /* CS3 */
171 0xc 0x01000000 0x0f000000
172 >;
173 };
174 spi1_pins: pinmux_spi1_pins {
175 pinctrl-single,bits = <
176 /* SIMO, SOMI, CLK */
177 0x14 0x00110100 0x00ff0f00
178 >;
179 };
180 spi1_cs0_pin: pinmux_spi1_cs0 {
181 pinctrl-single,bits = <
182 /* CS0 */
183 0x14 0x00000010 0x000000f0
184 >;
185 };
186 mdio_pins: pinmux_mdio_pins {
187 pinctrl-single,bits = <
188 /* MDIO_CLK, MDIO_D */
189 0x10 0x00000088 0x000000ff
190 >;
191 };
192 mii_pins: pinmux_mii_pins {
193 pinctrl-single,bits = <
194 /*
195 * MII_TXEN, MII_TXCLK, MII_COL
196 * MII_TXD_3, MII_TXD_2, MII_TXD_1
197 * MII_TXD_0
198 */
199 0x8 0x88888880 0xfffffff0
200 /*
201 * MII_RXER, MII_CRS, MII_RXCLK
202 * MII_RXDV, MII_RXD_3, MII_RXD_2
203 * MII_RXD_1, MII_RXD_0
204 */
205 0xc 0x88888888 0xffffffff
206 >;
207 };
208 lcd_pins: pinmux_lcd_pins {
209 pinctrl-single,bits = <
210 /*
211 * LCD_D[2], LCD_D[3], LCD_D[4], LCD_D[5],
212 * LCD_D[6], LCD_D[7]
213 */
214 0x40 0x22222200 0xffffff00
215 /*
216 * LCD_D[10], LCD_D[11], LCD_D[12], LCD_D[13],
217 * LCD_D[14], LCD_D[15], LCD_D[0], LCD_D[1]
218 */
219 0x44 0x22222222 0xffffffff
220 /* LCD_D[8], LCD_D[9] */
221 0x48 0x00000022 0x000000ff
222
223 /* LCD_PCLK */
224 0x48 0x02000000 0x0f000000
225 /* LCD_AC_ENB_CS, LCD_VSYNC, LCD_HSYNC */
226 0x4c 0x02000022 0x0f0000ff
227 >;
228 };
229 vpif_capture_pins: vpif_capture_pins {
230 pinctrl-single,bits = <
231 /* VP_DIN[2..7], VP_CLKIN1, VP_CLKIN0 */
232 0x38 0x11111111 0xffffffff
233 /* VP_DIN[10..15,0..1] */
234 0x3c 0x11111111 0xffffffff
235 /* VP_DIN[8..9] */
236 0x40 0x00000011 0x000000ff
237 >;
238 };
239 vpif_display_pins: vpif_display_pins {
240 pinctrl-single,bits = <
241 /* VP_DOUT[2..7] */
242 0x40 0x11111100 0xffffff00
243 /* VP_DOUT[10..15,0..1] */
244 0x44 0x11111111 0xffffffff
245 /* VP_DOUT[8..9] */
246 0x48 0x00000011 0x000000ff
247 /*
248 * VP_CLKOUT3, VP_CLKIN3,
249 * VP_CLKOUT2, VP_CLKIN2
250 */
251 0x4c 0x00111100 0x00ffff00
252 >;
253 };
254 };
255 prictrl: priority-controller@14110 {
256 compatible = "ti,da850-mstpri";
257 reg = <0x14110 0x0c>;
258 status = "disabled";
259 };
260 cfgchip: chip-controller@1417c {
261 compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
262 reg = <0x1417c 0x14>;
263
264 usb_phy: usb-phy {
265 compatible = "ti,da830-usb-phy";
266 #phy-cells = <1>;
267 status = "disabled";
268 };
269 };
270 edma0: edma@0 {
271 compatible = "ti,edma3-tpcc";
272 /* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */
273 reg = <0x0 0x8000>;
274 reg-names = "edma3_cc";
275 interrupts = <11 12>;
276 interrupt-names = "edma3_ccint", "edma3_ccerrint";
277 #dma-cells = <2>;
278
279 ti,tptcs = <&edma0_tptc0 7>, <&edma0_tptc1 0>;
280 };
281 edma0_tptc0: tptc@8000 {
282 compatible = "ti,edma3-tptc";
283 reg = <0x8000 0x400>;
284 interrupts = <13>;
285 interrupt-names = "edm3_tcerrint";
286 };
287 edma0_tptc1: tptc@8400 {
288 compatible = "ti,edma3-tptc";
289 reg = <0x8400 0x400>;
290 interrupts = <32>;
291 interrupt-names = "edm3_tcerrint";
292 };
293 edma1: edma@230000 {
294 compatible = "ti,edma3-tpcc";
295 /* eDMA3 CC1: 0x01e3 0000 - 0x01e3 7fff */
296 reg = <0x230000 0x8000>;
297 reg-names = "edma3_cc";
298 interrupts = <93 94>;
299 interrupt-names = "edma3_ccint", "edma3_ccerrint";
300 #dma-cells = <2>;
301
302 ti,tptcs = <&edma1_tptc0 7>;
303 };
304 edma1_tptc0: tptc@238000 {
305 compatible = "ti,edma3-tptc";
306 reg = <0x238000 0x400>;
307 interrupts = <95>;
308 interrupt-names = "edm3_tcerrint";
309 };
310 serial0: serial@42000 {
311 compatible = "ti,da830-uart", "ns16550a";
312 reg = <0x42000 0x100>;
313 reg-io-width = <4>;
314 reg-shift = <2>;
315 interrupts = <25>;
316 status = "disabled";
317 };
318 serial1: serial@10c000 {
319 compatible = "ti,da830-uart", "ns16550a";
320 reg = <0x10c000 0x100>;
321 reg-io-width = <4>;
322 reg-shift = <2>;
323 interrupts = <53>;
324 status = "disabled";
325 };
326 serial2: serial@10d000 {
327 compatible = "ti,da830-uart", "ns16550a";
328 reg = <0x10d000 0x100>;
329 reg-io-width = <4>;
330 reg-shift = <2>;
331 interrupts = <61>;
332 status = "disabled";
333 };
334 rtc0: rtc@23000 {
335 compatible = "ti,da830-rtc";
336 reg = <0x23000 0x1000>;
337 interrupts = <19
338 19>;
339 status = "disabled";
340 };
341 i2c0: i2c@22000 {
342 compatible = "ti,davinci-i2c";
343 reg = <0x22000 0x1000>;
344 interrupts = <15>;
345 #address-cells = <1>;
346 #size-cells = <0>;
347 status = "disabled";
348 };
349 i2c1: i2c@228000 {
350 compatible = "ti,davinci-i2c";
351 reg = <0x228000 0x1000>;
352 interrupts = <51>;
353 #address-cells = <1>;
354 #size-cells = <0>;
355 status = "disabled";
356 };
357 wdt: wdt@21000 {
358 compatible = "ti,davinci-wdt";
359 reg = <0x21000 0x1000>;
360 status = "disabled";
361 };
362 mmc0: mmc@40000 {
363 compatible = "ti,da830-mmc";
364 reg = <0x40000 0x1000>;
365 cap-sd-highspeed;
366 cap-mmc-highspeed;
367 interrupts = <16>;
368 dmas = <&edma0 16 0>, <&edma0 17 0>;
369 dma-names = "rx", "tx";
370 status = "disabled";
371 };
372 vpif: video@217000 {
373 compatible = "ti,da850-vpif";
374 reg = <0x217000 0x1000>;
375 interrupts = <92>;
376 status = "disabled";
377
378 /* VPIF capture port */
379 port@0 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 };
383
384 /* VPIF display port */
385 port@1 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 };
389 };
390 mmc1: mmc@21b000 {
391 compatible = "ti,da830-mmc";
392 reg = <0x21b000 0x1000>;
393 cap-sd-highspeed;
394 cap-mmc-highspeed;
395 interrupts = <72>;
396 dmas = <&edma1 28 0>, <&edma1 29 0>;
397 dma-names = "rx", "tx";
398 status = "disabled";
399 };
400 ehrpwm0: pwm@300000 {
401 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
402 "ti,am33xx-ehrpwm";
403 #pwm-cells = <3>;
404 reg = <0x300000 0x2000>;
405 status = "disabled";
406 };
407 ehrpwm1: pwm@302000 {
408 compatible = "ti,da850-ehrpwm", "ti,am3352-ehrpwm",
409 "ti,am33xx-ehrpwm";
410 #pwm-cells = <3>;
411 reg = <0x302000 0x2000>;
412 status = "disabled";
413 };
414 ecap0: ecap@306000 {
415 compatible = "ti,da850-ecap", "ti,am3352-ecap",
416 "ti,am33xx-ecap";
417 #pwm-cells = <3>;
418 reg = <0x306000 0x80>;
419 status = "disabled";
420 };
421 ecap1: ecap@307000 {
422 compatible = "ti,da850-ecap", "ti,am3352-ecap",
423 "ti,am33xx-ecap";
424 #pwm-cells = <3>;
425 reg = <0x307000 0x80>;
426 status = "disabled";
427 };
428 ecap2: ecap@308000 {
429 compatible = "ti,da850-ecap", "ti,am3352-ecap",
430 "ti,am33xx-ecap";
431 #pwm-cells = <3>;
432 reg = <0x308000 0x80>;
433 status = "disabled";
434 };
435 spi0: spi@41000 {
436 #address-cells = <1>;
437 #size-cells = <0>;
438 compatible = "ti,da830-spi";
439 reg = <0x41000 0x1000>;
440 num-cs = <6>;
441 ti,davinci-spi-intr-line = <1>;
442 interrupts = <20>;
443 dmas = <&edma0 14 0>, <&edma0 15 0>;
444 dma-names = "rx", "tx";
445 status = "disabled";
446 };
447 spi1: spi@30e000 {
448 #address-cells = <1>;
449 #size-cells = <0>;
450 compatible = "ti,da830-spi";
451 reg = <0x30e000 0x1000>;
452 num-cs = <4>;
453 ti,davinci-spi-intr-line = <1>;
454 interrupts = <56>;
455 dmas = <&edma0 18 0>, <&edma0 19 0>;
456 dma-names = "rx", "tx";
457 status = "disabled";
458 };
459 usb0: usb@200000 {
460 compatible = "ti,da830-musb";
461 reg = <0x200000 0x1000>;
462 ranges;
463 interrupts = <58>;
464 interrupt-names = "mc";
465 dr_mode = "otg";
466 phys = <&usb_phy 0>;
467 phy-names = "usb-phy";
468 status = "disabled";
469
470 #address-cells = <1>;
471 #size-cells = <1>;
472
473 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
474 &cppi41dma 2 0 &cppi41dma 3 0
475 &cppi41dma 0 1 &cppi41dma 1 1
476 &cppi41dma 2 1 &cppi41dma 3 1>;
477 dma-names =
478 "rx1", "rx2", "rx3", "rx4",
479 "tx1", "tx2", "tx3", "tx4";
480
481 cppi41dma: dma-controller@201000 {
482 compatible = "ti,da830-cppi41";
483 reg = <0x201000 0x1000
484 0x202000 0x1000
485 0x204000 0x4000>;
486 reg-names = "controller",
487 "scheduler", "queuemgr";
488 interrupts = <58>;
489 #dma-cells = <2>;
490 #dma-channels = <4>;
491 status = "okay";
492 };
493 };
494 sata: sata@218000 {
495 compatible = "ti,da850-ahci";
496 reg = <0x218000 0x2000>, <0x22c018 0x4>;
497 interrupts = <67>;
498 status = "disabled";
499 };
500 mdio: mdio@224000 {
501 compatible = "ti,davinci_mdio";
502 #address-cells = <1>;
503 #size-cells = <0>;
504 reg = <0x224000 0x1000>;
505 status = "disabled";
506 };
507 eth0: ethernet@220000 {
508 compatible = "ti,davinci-dm6467-emac";
509 reg = <0x220000 0x4000>;
510 ti,davinci-ctrl-reg-offset = <0x3000>;
511 ti,davinci-ctrl-mod-reg-offset = <0x2000>;
512 ti,davinci-ctrl-ram-offset = <0>;
513 ti,davinci-ctrl-ram-size = <0x2000>;
514 local-mac-address = [ 00 00 00 00 00 00 ];
515 interrupts = <33
516 34
517 35
518 36
519 >;
520 status = "disabled";
521 };
522 usb1: usb@225000 {
523 compatible = "ti,da830-ohci";
524 reg = <0x225000 0x1000>;
525 interrupts = <59>;
526 phys = <&usb_phy 1>;
527 phy-names = "usb-phy";
528 status = "disabled";
529 };
530 gpio: gpio@226000 {
531 compatible = "ti,dm6441-gpio";
532 gpio-controller;
533 #gpio-cells = <2>;
534 reg = <0x226000 0x1000>;
535 interrupts = <42 IRQ_TYPE_EDGE_BOTH
536 43 IRQ_TYPE_EDGE_BOTH 44 IRQ_TYPE_EDGE_BOTH
537 45 IRQ_TYPE_EDGE_BOTH 46 IRQ_TYPE_EDGE_BOTH
538 47 IRQ_TYPE_EDGE_BOTH 48 IRQ_TYPE_EDGE_BOTH
539 49 IRQ_TYPE_EDGE_BOTH 50 IRQ_TYPE_EDGE_BOTH>;
540 ti,ngpio = <144>;
541 ti,davinci-gpio-unbanked = <0>;
542 status = "disabled";
543 interrupt-controller;
544 #interrupt-cells = <2>;
545 };
546 pinconf: pin-controller@22c00c {
547 compatible = "ti,da850-pupd";
548 reg = <0x22c00c 0x8>;
549 status = "disabled";
550 };
551
552 mcasp0: mcasp@100000 {
553 compatible = "ti,da830-mcasp-audio";
554 reg = <0x100000 0x2000>,
555 <0x102000 0x400000>;
556 reg-names = "mpu", "dat";
557 interrupts = <54>;
558 interrupt-names = "common";
559 status = "disabled";
560 dmas = <&edma0 1 1>,
561 <&edma0 0 1>;
562 dma-names = "tx", "rx";
563 };
564
565 lcdc: display@213000 {
566 compatible = "ti,da850-tilcdc";
567 reg = <0x213000 0x1000>;
568 interrupts = <52>;
569 max-pixelclock = <37500>;
570 status = "disabled";
571 };
572 };
573 aemif: aemif@68000000 {
574 compatible = "ti,da850-aemif";
575 #address-cells = <2>;
576 #size-cells = <1>;
577
578 reg = <0x68000000 0x00008000>;
579 ranges = <0 0 0x60000000 0x08000000
580 1 0 0x68000000 0x00008000>;
581 status = "disabled";
582 };
583 memctrl: memory-controller@b0000000 {
584 compatible = "ti,da850-ddr-controller";
585 reg = <0xb0000000 0xe8>;
586 status = "disabled";
587 };
588};